SLG47503 datasheet(28/191 Pages) DIALOG

28 / 191 page

Datasheet

16-Jul-2021

CFR0011-120-00

Revision 2.0

28 of 191

SLG47502/03

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

5.7 MATRIX OE IO STRUCTURE

5.7.1 Matrix OE IO Structure (from GPIO0 to GPIO11)

Figure 5: Matrix OE IO Structure Diagram

Digital OUT

PP1x_EN

Digital OUT

PP2x_EN

Digital OUT

OD1x_EN

Digital OUT

OD2x_EN

2 k

(Note 2)

LV_EN

SMT_EN

WOSMT_EN

Digital IN

Analog IO

900 k

90 k

8 k

Floating

Pull-up_EN

Res_sel [1:0]

00: Floating

01: 10 k

10: 100 k

11: 1 M

Non-Schmitt

Trigger Input

Schmitt

Trigger Input

Low Voltage

Input

Input Mode [1:0]

00: Digital In without Schmitt Trigger, wosmt_en = 1

01: Digital In with Schmitt Trigger, smt_en = 1

10: Low Voltage Digital In mode, lv_en = 1

11: analog IO mode

Output Mode [1:0]

00: Push-Pull 1x mode, pp1x_en = 1

01: Push-Pull 2x mode, pp2x_en = 1, pp1x_en = 1

10: NMOS 1x Open-Drain mode, od1x_en = 1

11: NMOS 2x Open-Drain mode, od2x_en = 1, od1x_en = 1

Note 1: Digital Out and OE are Matrix Output, Digital In is Matrix Input

Note 2: Can be varied over PVT, for reference only.

VDD

PAD

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