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SLG47503 Datasheet(PDF) 85 Page - Dialog Semiconductor |
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SLG47503 Datasheet(HTML) 85 Page - Dialog Semiconductor |
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85 / 191 page  Datasheet 16-Jul-2021 CFR0011-120-00 Revision 2.0 85 of 191 © 2021 Dialog Semiconductor SLG47502/03 Low Voltage GreenPAK Programmable Mixed-Signal Matrix Preliminary Figure 68: Wake/Sleep Controller OSC CK_OSC Divider CNT_end Power Control From Connection Matrix Output [96] for 2 kHz OSC0 Analog Control Block registers [907:904] WS_PD to W&S out state selection register [947] WS clock freq. selection registers [927:912] WS ratio control data register [949] ACMPs_PD WS_out bg/regulator pdb ACMPH0,1 OUT To Connection Matrix Input [60, 61] From Connection Matrix Output [94:93] WS_out Note: WS_PD is High at WS OSC (2 kHz OSC0) power-down WS Controller CNT0_out To Connection Matrix Input [16] ck CNT 2 ACMPs_PD + - ACMPx WS EN: registers [953:952] 0 1 BG/Analog_Good ACMPs 2 2 WS_PD (from OSC PD) WS_PD 2 WS_out WS mode: normal or short wake |
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