SLG47503 datasheet(46/191 Pages) DIALOG

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Datasheet

16-Jul-2021

CFR0011-120-00

Revision 2.0

46 of 191

SLG47502/03

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

This macrocell, when programmed for a LUT function, uses a 4-bit register to define their output function:

2-Bit LUT2_3 is defined by registers [647:644]

Table 25 shows the register bits for the standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR) that can be created

within each of the 2-bit LUT logic cells.

7.3 3-BIT LUT OR D FLIP-FLOP WITH SET/RESET OR SHIFT REGISTER MACROCELLS

There are ten macrocells that can serve as 3-bit LUT or as DFF/LATCH, or as Shift Register. It is also possible to define the active

level (Q or nQ) for the macrocell’s output by registers [766], [774], [782], [790], [798], [806], [814], [822], [830], [838]. DFF/Shift

Register or LUT are selected by registers [761], [769], [777], [785], [793], [801], [809], [817], [825], [833]. When used to implement

LUT functions, the 3-bit LUT takes in three input signals from the connection matrix and produces a single output, which goes

back into the connection matrix.

When used to implement Shift Register, the three input signals from the connection matrix go to the data (D_in), clock (CLK), and

Set/Reset (nSET/nRST) inputs for the Shift Register, with the output going back to the connection matrix. It is possible to define

the active level for the Set/Reset input of Shift Register macrocell which is selected by registers [768], [776], [784], [792], [800],

[808], [816], [824], [832], [840]. The input data (D_in) writes into LSB. The Shift Register length (up to 8 bits/memory cells) is

selected by registers [764:762], [772:770], [780:778], [788:786], [796:794], [804:802]. [812:810], [820:818], [828:826], [836:834],

[845:842], when these registers = 0 DFF/LATCH function is selected.

When used to implement D Flip-Flop/LATCH function, the three input signals from the connection matrix go to the data (D_in),

clock (CLK), and Set/Reset (nSET/nRST) inputs for the Flip-Flop/LATCH, with the output going back to the connection matrix. It

is possible to define the active level for the Set/Reset input (nSET/nRST_sel which is selected by register [767], [775], [783],

[791], [799], [807], [815], [823], [831], [839]) of DFF/LATCH macrocell. LATCH or DFF configuration is selected by registers [765],

[773], [781], [789], [797], [805], [813], [821], [829], [837].

The operation of the D Flip-Flop and LATCH will follow the functional descriptions below:

DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change.

LATCH: when CLK is Low, then Q = D; otherwise Q remains its previous value (input D has no effect on the output, when CLK

is High)

Table 25: 2-bit LUT Standard Digital Functions

Function

MSB

LSB

AND-2

NAND-2

OR-2

NOR-2

XOR-2

XNOR-2

Table 24: 2-bit LUT2_3 Truth Table

IN1

IN0

OUT

LSB

MSB

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