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SLG47503 Datasheet(PDF) 75 Page - Dialog Semiconductor |
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SLG47503 Datasheet(HTML) 75 Page - Dialog Semiconductor |
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75 / 191 page ![]() Datasheet 16-Jul-2021 CFR0011-120-00 Revision 2.0 75 of 191 © 2021 Dialog Semiconductor SLG47502/03 Low Voltage GreenPAK Programmable Mixed-Signal Matrix Preliminary 8.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY7 Figure 52: Delay Mode Timing Diagram (Rising, Falling, and Both Edge Detection) Figure 53: Counter Mode Timing Diagram without Two DFFs Synced Up One-Shot/Freq. DET/Delay IN Delay Function Rising Edge Detection Delay Function Falling Edge Detection Delay Function Both Edge Detection t t t t Delay time Delay time Delay time Delay time Delay time Delay time RESET_IN CLK Counter OUT Count start in first rising edge CLK 4 CLK period pulse |
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