SLG47503 datasheet(32/191 Pages) DIALOG

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Datasheet

16-Jul-2021

CFR0011-120-00

Revision 2.0

32 of 191

SLG47502/03

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

Connection Matrix

The Connection Matrix in the SLG47502/03 is used to create an internal routing for internal functional macrocells of the device

once it is programmed. The registers are programmed from the one time programmable (OTP) NVM cell during Test Mode

Operation. The output of each functional macrocell within the SLG47502/03 has a specific digital bit code assigned to it, that is

either set to active “High” or inactive “Low”, based on the design that is created. Once the 2048 register bits within the SLG47502/

03 are programmed, a fully custom circuit will be created.

The Connection Matrix has 64 inputs and 98 outputs. Each of the 64 inputs to the Connection Matrix is hard-wired to the digital

output of a particular source macrocell, including IO pins, LUTs, analog comparators, other digital resources, such as VDD and

GND. The input to a digital macrocell uses a 6-bit register to select one of these 64 input lines.

For a complete list of the SLG47502/03’s register table, see Section 17.

Figure 11: Connection Matrix

Figure 12: Connection Matrix Usage Example

GND

LUT2_0/DFF0 output/

Shift_Reg0 output

Matrix Input Signal

Functions

POR

VDD

Function

Registers

Matrix Out: Oscillator1

ENABLE

registers [627:622]

Matrix OUT: IN0 of

LUT2_0 or Clock In-

put of DFF0 or Clock

Input of Shift_Reg0

registers [45:40]

Matrix OUT: IN1 of

LUT2_0 or Data In-

put of DFF0 or Data

Input of Shift_Reg0

registers [51:46]

Matrix Out: IN0 of

LUT2_1 or Clock In-

put of DFF1 or Clock

Input of Shift_Reg1

registers [57:52]

Matrix Inputs

Matrix Outputs

LUT2_1/DFF1 output/

Shift_Reg1 output

LUT2_2/DFF2 output/

Shift_Reg2 output

GPIO7

GPIO8

GPIO9

Connection Matrix

LUT

GPIO8

GPIO7

LUT

GPIO9

Function

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