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SLG47503 Datasheet(PDF) 52 Page - Dialog Semiconductor |
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SLG47503 Datasheet(HTML) 52 Page - Dialog Semiconductor |
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52 / 191 page ![]() Datasheet 16-Jul-2021 CFR0011-120-00 Revision 2.0 52 of 191 © 2021 Dialog Semiconductor SLG47502/03 Low Voltage GreenPAK Programmable Mixed-Signal Matrix Preliminary Figure 30: 3-bit LUT9 or DFF12 or Shift Register 12 Figure 31: DFF3 to DFF12 and Shift Register 3 to Shift Register 12 Operation 3 8 memory cells D_in Clk nSET/nRST SET/RST S1 S0 000 111 . . . [7] 3-bit LUT S0 S1 S1 S0 S0 S1 S0 S1 From Connectinon Matrix Output [36] 3 ShRg/LUT_sel Out[7:0] 8 3 7 4 LATCH/DFF_sel nSET/nRST_sel To Connection Matrix Input [14] ShRg_length [2:0] 1-bit NVM 7-bit NVM LUT IN1 DFF data in ShRg data in LUT IN0 DFF CLK ShRg CLK From Connectinon Matrix Output [35] From Connectinon Matrix Output [37] LUT IN2 DFF nSet/nRST ShRg nSet/nRST LUT config nQ/Q_sel SET/RST_act_level VDD Data Clk POR Initial Value 10011011 (x9B) 00110111 01101111 11011110 10111100 01111000 11110000 11100000 11000001 10000011 00000111 Q=ShReg_Out[0] (see note 1) Q=ShReg_Out[7] (see note 2) ShReg_Out[7:0] (Internal Signal) Note1 : Macrocell is configured as DFF Note2 : Macrocell is configured as 8-bit Shift Register 00001111 Initial Value is transmitted (x9B) Inital Value is loaded from NVM to Shift Register x9 xB Input Data are transmitted MSB LSB |
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