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SLG47503 Datasheet(PDF) 84 Page - Dialog Semiconductor |
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SLG47503 Datasheet(HTML) 84 Page - Dialog Semiconductor |
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84 / 191 page ![]() Datasheet 16-Jul-2021 CFR0011-120-00 Revision 2.0 84 of 191 © 2021 Dialog Semiconductor SLG47502/03 Low Voltage GreenPAK Programmable Mixed-Signal Matrix Preliminary 8.5 WAKE AND SLEEP CONTROLLER SLG47502/03 has a Wake and Sleep function for all ACMPs. The macrocell CNT/DLY0 can be reconfigured for this purpose registers [953:952] = 11 and register [948] = 1. The WS serves for power saving, it allows to switch on and off selected ACMPs on selected bit of 16-bit counter. Note 1: BG/Analog_Good time is long and should be considered in wake and sleep timing in case it dynamically powers on/off. Note 2: Wake time should be long enough to make sure ACMP and Vref have enough time to get a sample before going to sleep. Figure 66: Freq. Detector/FSM Mode, Rising Edge, OSC is Forced On, DFFs Synced Up, UP = 0, CNT Data = 3 Figure 67: Delayed Edge Detector/FSM Mode, Rising Edge, OSC is Forced On, DFFs Synced Up, UP = 0, CNT Data = 3 Delay In Clk 3 Q 2 3 2 Keep Internal Counter 2 Less than 3 clk between 2 rising edges 3 1 3 Two extra clocks Two extra clocks Delay In Clk 3 Q Keep Internal Counter 1 3 2 2 1 3 Two extra clocks Two extra clocks Time less than CNT Data doesn’t cause any change |
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