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SLG47503 Datasheet(PDF) 69 Page - Dialog Semiconductor |
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SLG47503 Datasheet(HTML) 69 Page - Dialog Semiconductor |
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69 / 191 page ![]() Datasheet 16-Jul-2021 CFR0011-120-00 Revision 2.0 69 of 191 © 2021 Dialog Semiconductor SLG47502/03 Low Voltage GreenPAK Programmable Mixed-Signal Matrix Preliminary As shown in Figures 22-28 there is a possibility to use LUT/DFF and CNT/DLY simultaneously. Note: It is not possible to use LUT and DFF at once, one of these macrocells must be selected. Case 1. LUT/DFF in front of CNT/DLY. Three input signals from the connection matrix go to previously selected LUT or DFF's inputs and produce a single output which goes to a CND/DLY input. In its turn Counter/Delay's output goes back to the matrix. Case 2. CNT/DLY in front of LUT/DFF. Two input signals from the connection matrix go to CND/DLY's inputs (IN and CLK). Its output signal can be connected to any input of previously selected LUT or DFF, after which the signal goes back to the matrix. Case 3. Single LUT/DFF or CNT/DLY. Also, it is possible to use a standalone LUT/DFF or CNT/DLY. In this case, all inputs and output of the macrocell are connected to the matrix. Figure 49: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT16/DFF21, CNT/DLY7) CNT/DLY7 OUT ext_CLK DLY_IN/CNT Reset 3-bit LUT16 OUT IN0 IN1 8-bits NVM IN2 registers [1255:1248] From Connection Matrix Output [66] To Connection Matrix Input [30] LUT Truth Table CNT Data S0 S1 Config Data CLK D Q/nQ DFF Registers From Connection Matrix Output [65] S0 S1 From Connection Matrix Output [64] S0 S1 S0 S1 S0 S1 S2 S3 registers [1287:1280] nRST/nSET To Connection Matrix Input [31] S0 S1 S0 S1 S0 S1 0 S0 S1 S2 S3 0 LUT/DFF Sel registers [1267:1264] register [1260] Mode Sel register [1248] DFF or Latch Select register [1249] Output Select (Q or nQ) register [1250] DFF Initial Polarity Se- lect register [1251] (nRST or nSET) from matrix Output DFF/ Latch21 registers [1275:1272], [1269:1268], [1263:1261], [1259:1255] |
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