ATXP032 datasheet(103/113 Pages) DIALOG

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101

ATXP032

DS-ATXP032–114I–4-2020

Figure 14-2. Overshoot / Undershoot Definition

14.10 Input Test Waveforms and Measurement Levels

14.11 Output Test Load

15.

Power-On / Reset State

When power is first applied to the device, or when recovering from a reset condition, the output pin (SO) is in a high

impedance state, and a high-to-low transition on the CS pin is required to start a valid instruction. The SPI mode (3

or 0) is automatically selected on every falling edge of CS by sampling the inactive clock state.

15.1

Power-Up/Power-Down Voltage and Timing Requirements

As the device initializes, there is a transient current demand. The system needs to be capable of providing this

current to ensure correct initialization. During power-up, the device must not be READ for at least the minimum

VCSL time after the supply voltage reaches the minimum VCC level (VCC min). While the device is being powered-

up, the internal Power-on Reset (POR) circuitry keeps the device in a reset mode until the supply voltage rises

above the minimum V

CC. During this time, all operations are disabled and the device does not respond to any

commands. The internal reset level, V

POR, is lower than VCC min. However, the tVCSL time is measured from when

CC reaches VCC min.

If the first operation to the device after power-up is a program or erase operation, then the operation cannot be

started until the supply voltage reaches the minimum V

CC level and an internal device delay has elapsed. This

delay is a maximum time of t

PUW. After the tPUW time, the device is placed in standby mode if CS is at logic high or

active mode if CS is at logic low. For the case of power-down then power-up operation, or if a power interruption

GND

Voltage

Time

Undershoot Area

Overshoot Area

Maximum Amplitude

DRIVING

LEVELS

MEASUREMENT

LEVEL

0.1V

CC/2

0.9V

tR, tF < 2 ns (10% to 90%)

Device

Under

Test

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