P5021 datasheet(132/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Hardware design considerations

Freescale Semiconductor

132

3.1.4

Core complex PLL select

The clock frequency of each of the core 0–1 complex is determined by the binary value of the RCW field Cn_PLL_SEL. This

table describes the supported ratios for each core complex 0-1, where each individual core complex can select a frequency from

the table.

3.1.5

DDR controller PLL ratios

The dual DDR memory controller complexes can be synchronous with or asynchronous to the platform, depending on

configuration. Both DDR controllers operate at the same frequency configuration.

Table 98 describes the clock ratio between the DDR memory controller PLLs and the externally supplied SYSCLK input

(asynchronous mode) or from the platform clock (synchronous mode).

In asynchronous DDR mode, the DDR data rate to SYSCLK ratios supported are listed in Table 98. This ratio is determined by

the binary value of the RCW Configuration field MEM_PLL_RAT[10:14]. The corresponding setting for

MEM_PLL_CFG[0:1] is listed in Table 99.

NOTE

The RCW Configuration field DDR_SYNC (bit 184) must be set to b’0 for asynchronous

mode, and b’1 for synchronous mode.

The RCW Configuration field DDR_RATE (bit 232) must be set to b’0 for asynchronous

mode, and b’1 for synchronous mode.

The RCW Configuration field DDR_RSV0 (bit 234) must be set to b’0 for all ratios.

Table 97. Core complex [0,

1] PLL select

Binary value of Cn_PLL_SEL

Core cluster ratio

0000

CC1 PLL /1

0001

CC1 PLL /2

0100

CC2 PLL /1

0101

CC2 PLL/2

All Others

Reserved

Note: If CC2 PLL is used by core0 or core1, then CC2 PLL must be operated

at a lower frequency than the CC1 PLL, and its maximum allowed

frequency is 80% of the maximum rated frequency of the core at nominal

voltage.

Table 98. Asynchronous DDR clock ratio

Binary value of MEM_PLL_RAT[10:14]

DDR:SYSCLK ratio

0_0101

5:1

0_0110

6:1

0_1000

8:1

0_1001

9:1

0_1010

10:1

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