P5021 datasheet(135/155 Pages) NXP

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Hardware design considerations

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

135

Note that “PCI Express link width” in the above equation refers to the negotiated link width as the result of PCI Express link

training, which may or may not be the same as the link width POR selection.

3.1.7

SerDes PLL ratio

The clock ratio between each of the four SerDes PLLs and their respective externally supplied

SD_REF_CLKn/SD_REF_CLKn inputs is determined by the binary value of the RCW Configuration field SRDS_RATIO_Bn

as shown in this table. Furthermore, each SerDes lane grouping can be run at a SerDes PLL frequency divider determined by

the binary value of the RCW field SRDS_DIV_Bn as shown in Table 103 and Table 104.

This table lists the supported SerDes PLL Bank n to SD_REF_CLKn ratios.

This table shows the PLL divider support for each pair of lanes on SerDes Bank 1.

This table shows the PLL dividers supported for each 4 lane group for SerDes Banks 2, 3, and 4.

Table 102. SerDes PLL bank n to SD_REF_CLKn ratios

Binary value of

SRDS_RATIO_Bn

SRDS_PLL_n:SD_REF_CLKn ratio

n = 1 (bank 1) n = 2 (bank 2) n = 3 (bank 3) n = 4(bank 4)

001

Reserved

20:1

Reserved

010

25:1

Reserved

011

40:1

Reserved

100

50:1

Reserved

101

Reserved

24:1

110

Reserved

30:1

All Others

Reserved

Table 103. SerDes bank 1 PLL dividers

Binary value of SRDS_DIV_B1[0:4] SerDes bank 1 PLL divider

0b0

Divide by 1 off Bank 1 PLL

0b1

Divide by 2 off Bank 1 PLL

Note:

1. 1 bit (of 5 total SRDS_DIV_B1 bits) controls each pair of lanes,

where the first bit controls configuration of lanes A/B (or 0/1) and

the last bit controls configuration of lanes I/J (or 8/9).

Table 104. SerDes banks 2, 3, and 4 PLL dividers

Binary value of SRDS_DIV_Bn SerDes Bank n PLL divider

0b0

Divide by 1 off Bank n PLL

0b1

Divide by 2 off Bank n PLL

Notes:

1. One bit controls all 4 lanes of each bank.

2. n = 2 or 3 (SerDes bank 2 or bank 3)

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