P5021 datasheet(138/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Hardware design considerations

Freescale Semiconductor

138

Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from

nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the

footprint, without the inductance of vias.

Figure 51 shows the PLL power supply filter circuit.

Where:

R = 5

Ω ± 5%

C1 = 10

μF ± 10%, 0603, X5R, with ESL ≤ 0.5 nH

C2 = 1.0

μF ± 10%, 0402, X5R, with ESL ≤ 0.5 nH

NOTE

A higher capacitance value for C2 may be used to improve the filter as long as the other C2

parameters do not change (0402 body, X5R, ESL

≤ 0.5 nH).

Voltage for AVDD is defined at the PLL supply filter and not the pin of AVDD.

Figure 51. PLL power supply filter circuit

The AVDD_SRDSn signals provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock,

the power supplied to the PLL is filtered using a circuit similar to the one shown in following Figure 52. For maximum

effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDSn balls to ensure it filters out as much noise as

possible. The ground connection should be near the AVDD_SRDSn balls. The 0.003-µF capacitor is closest to the balls, followed

by two 2.2-µF capacitors, and finally the 1-

Ω resistor to the board supply plane. The capacitors are connected from AVDD_SRDSn

to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces should be kept

short, wide, and direct.

Figure 52. SerDes PLL power supply filter circuit

Note the following:

•AVDD_SRDSn should be a filtered version of SVDD.

•

Signals on the SerDes interface are fed from the XVDD power plane.

•

Voltage for AVDD_SRDSn is defined at the PLL supply filter and not the pin of AVDD_SRDSn.

•

An 0805 sized capacitor is recommended for system initial bring-up.

3.3.2

XVDD power supply filtering

XVDD may be supplied by a linear regulator or sourced by a filtered 1.5 V or 1.8 V voltage source. Systems may design in both

options to allow flexibility to address system noise dependencies.

An example solution for XVDD filtering, where 1.5 V or 1.8 V is sourced from voltage source (for example, GVDD at 1.5 V

when using DDR3, or CVDD at 1.8 V), is illustrated in Figure 53. The component values in this example filter is system

VDD_PL

AVDD_PLAT, AVDD_CCn, AVDD_DDR

GND

Low ESL Surface Mount Capacitors

AVDD_FM

2.2 µF1

0.003 µF

1.0

AVDD_SRDSn

2.2 µF1

GND

SVDD

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