P5021 datasheet(139/155 Pages) NXP

139 / 155 page

Hardware design considerations

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

139

dependent and are still under characterization, component values may need adjustment based on the system or environment

noise.

Where:

C1 = 2.2

μF ± 10%, X5R, with ESL ≤ 0.5 nH

C2 = 2.2

μF ± 10%, X5R, with ESL ≤ 0.5 nH

F1 = 120

Ω at 100-MHz 2A 25% 0603 Ferrite

F2 = 120

Ω at 100-MHz 2A 25% 0603 Ferrite

Bulk and decoupling capacitors are added, as needed, per power supply design.

Figure 53. XVDD power supply filter circuit

3.3.3

USB_VDD_1P0 power supply filtering

USB_VDD_1P0 should be sourced by a filtered VDD_PL using a star connection. An example solution for USB_VDD_1P0

filtering, where USB_VDD_1P0 is sourced from VDD_PL, is illustrated in Figure 54. The component values in this example filter

is system dependent and are still under characterization, component values may need adjustment based on the system or

environment noise.

Where:

C1 = 2.2

μF ± 20%, X5R, with Low ESL (for example, Panasonic ECJ0EB0J225M)

F1 = 120

Ω at 100-MHz 2A 25% Ferrite (for example, Murata BLM18PG121SH1)

Bulk and decoupling capacitors are added, as needed, per power supply design.

Figure 54. USB_VDD_1P0 power supply filter circuit

3.4

Decoupling recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high

frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching

other components in the chip’s system, and the chip itself requires a clean, tightly regulated source of power. Therefore, it is

recommended that the system designer place at least one decoupling capacitor at each VDD, BVDD, OVDD, CVDD, GVDD, and

LVDD pin of the chip. These decoupling capacitors should receive their power from separate VDD, BVDD, OVDD, CVDD,

GVDD, LVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed

directly under the device using a standard escape pattern. Others may surround the part.

These capacitors should have a value of 0.01 or 0.1

μF. Only ceramic SMT (surface mount technology) capacitors should be

used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, BVDD,

OVDD, CVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should

XVDD

1.5 V or 1.8V source

GND

Bulk and

Decoupling

Capacitors

USB_VDD_1P0

VDD_PL

GND

Bulk and

Decoupling

Capacitors

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