P5021 datasheet(140/155 Pages) NXP

140 / 155 page

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Hardware design considerations

Freescale Semiconductor

140

have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected

to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS

tantalum or Sanyo OSCON).

3.5

SerDes block power supply decoupling recommendations

The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low jitter on transmit and

reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below.

Only SMT capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be

done with multiple vias to further reduce inductance.

•

First, the board should have at least 10

× 10-nF SMT ceramic chip capacitors as close as possible to the supply balls

of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and

ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the

chip as close to the supply and ground connections as possible.

•

Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be done for all SerDes

supplies.

•

Third, between the device and any SerDes voltage regulator there should be a 10-µF, low ESR SMT tantalum chip

capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies.

3.6

Connection recommendations

To ensure reliable operation, it is recommended the user consider the following:

•

Connect unused inputs to an appropriate signal level. All unused active low inputs should be tied to VDD, BVDD,

CVDD, OVDD, GVDD, and LVDD as required. All unused active high inputs should be connected to GND. All NC (no

connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, BVDD,

CVDD, OVDD, GVDD, LVDD, and GND pins of the chip.

•

The Ethernet controllers 1 and/or 2 input pins may be disabled by setting their respective RCW Configuration field

EC1 (bits 360–361), and EC2 (bits 363–364), to 0b11 = No parallel mode Ethernet. When disabled, these inputs do

not need to be externally pulled to an appropriate signal level.

•ECn_GTX_CLK125 is a 125-MHz input clock on the dTSEC ports. If the dTSEC ports are not used for RGMII, the

ECn_GTX_CLK125 input can be tied off to GND.

•

If RCW field DMA1=0b1 (RCW bit 384), the DMA1 external interface is not enabled and this pin should be left as a

no connect.

•

If RCW field I2C = 0b100 or 0b101 (RCW bits 355–357), the SDHC_WP and SDHC_CD input signals are enabled

for external use. If SDHC_WP and SDHC_CD are selected and not used, they must be externally pulled low such that

SDHC_WP = 0 (write enabled) and SDHC_CD = 0 (card detected). If RCW field I2C != 0b100 or 0b101, thereby

selecting either I2C3 or GPIO functionality, SDHC_WP and SDHC_CD are internally driven such that SDHC_WP =

write enabled and SDHC_CD = card detected and the selected I2C3 or GPIO external pin functionality may be used.

•

.For P5021 (SVR = 0x8205_00XX) or P5021E (SVR = 0x820D_00XX), TEST_SEL must be connected to GND.

•

The TMP_DETECT pin is an active low input to the Security Monitor (see Chapter “Secure Boot and Trust

Architecture” in the applicable chip reference manual). When using Trust Architecture functionality, external logic

must ramp TMP_DETECT with OVDD. If not using Trust Architecture functionality, TMP_DETECT must be tied to

OVDD to prevent the input from going low.

3.6.1

Legacy JTAG configuration signals

Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 56.

Care must be taken to ensure that these pins are maintained at a valid negated state under normal operating conditions as most

have asynchronous behavior and spurious assertion gives unpredictable results.

P5021 Datasheet(PDF) 140 Page - NXP Semiconductors

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