VIA Technologies, Inc.
Preliminary VT6508 Datasheet
-11-
PIN DESCRIPTIONS
No.
Name
Type
Description
RMII interface
See Fig. 2 CSDV[7:0]
I
Carries sense and data valid from port 7 to port 0 :
See Fig. 2 RXD0[7:0]
I
Receive data zero from port 7 to port 0 :
See Fig. 2 RXD1[7:0]
I
Receive data one from port 7 to port 0 :
See Fig. 2 TXEN[7:0]
O
Transmit enable from port 7 to port 0 :
See Fig. 2 TXD0[7:0]
O
Transmit data zero from port 7 to port 0 :
See Fig. 2 TXD1[7:0]
O
Transmit data one from port 7 to port 0 :
SRAM Interface
See Fig. 2 SA[15:1]
O
SRAM Address Bus:
15-bit SDRAM data bus. These signals connect directly to the address
input of the SDRAM devices.
See Fig. 2
SOE
O
Output Enable
See Fig. 2
SWE
O
SRAM Write Enable
See Fig. 2
SADS
O
Synchronous Processor Address Status
See Fig. 2 SD[31:0]
I/O
SRAM Data:
32-bit SRAM data bus. These signals connect directly to the data
input/output pins of the SRAM devices.
Miscellaneous Interface
See Fig. 2 EEC/LEDC
O
Serial EEPROM Interface Clock (if strapping SD25 is default high)
The on-board EEPROM device address must be 1010 001 XXXXXXXX.
Serial LED Serial-Out Clock (if strapping SD25 is low)
The LEDC is 1MHz and has a burst per 50ms.
See Fig. 2 EEIO/LEDIO
I/O
Serial EEPROM Interface Data (if strapping SD25 is default high)
Serial LED Serial-Out Data Output (if strapping SD25 is low)
See Fig. 2 MDC
O
Management Interface (MI) Clock Output
See Fig. 2 MDIO
I/O
Management Interface (MI) Data I/O
See Fig. 2 RCLK50
I
50MHz Main Reference Clock
See Fig. 2 SCLK
I
SRAM Reference Clock
The suggested clock rate is 83MHz or more high for non-blocking
requirement.
See Fig. 2
RESET
I
SYSTEM RESET
Power Supply & Ground
See Fig. 2 VDD
P
Positive 3.3V supply to the core digital logic.
See Fig. 2 VCC
P
Positive 3.3V supply to all I/O pads.
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