VIA Technologies, Inc.
Preliminary VT6508 Datasheet
-40-
12H
Packet Data Register
Write this register (need to cooperate with
WR_PKT_CMD at 0610H and
WR_PKT_STATUS at 1910H) to send an
incoming-to-switch packet to CPU Input Control.
Read this register (need to cooperate with
PKT_BYTE_CNT at 1900-1901H and
RD_PKT_STATUS at 1902H) to retrieve an
outgoing-from-switch packet from CPU Output
Control.
Note that any read or write to this register will not
cause auto-increment of the Address Register to
support the continuous packet-byte read/write
commands.
The cpu interface with external is 8bit bus.
However the interface between cpuif and cpuioctl
is 16bit data bus. Reading packet data will be
served by cpuioctl so that it will know all the 16bit
are valid or only 8 bit are valid data. For cpu to
read packet, please read one more dummy byte
after reading the last byte if the packet length is
even.
PKT_DATA
[7:0]
R/W
13H
bits [47:40] of switch MAC address [47:0]
SWITCH_MAC
[7:0]
00H
R/W
14H
bits [39:32] of switch MAC address [47:0]
SWITCH_MAC
[7:0]
40H
R/W
15H
bits [31:24] of switch MAC address [47:0]
SWITCH_MAC
[7:0]
63H
R/W
16H
bits [23:16] of switch MAC address [47:0]
SWITCH_MAC
[7:0]
80H
R/W
17H
bits [15:8] of switch MAC address [47:0]
SWITCH_MAC
[7:0]
00H
R/W
18H
bits [7:0] of switch MAC address [47:0]
SWITCH_MAC
[7:0]
00H
R/W
19H
trigger/check SRAM auto test
Write to this register will trigger the SRAM auto-
test function.
The status of execution of the SRAM auto-test
function is reported in this register, defined as
follows:
bit 2: 1
→ in progress, 0 → complete or idle
bit 1: 1
→ error in single r/w connectivity,
0
→ no error in single r/w connectivity
bit 0: 1
→ error in burst r/w connectivity,
0
→ no error in burst r/w connectivity
SRAM_AUTO_TEST [2:0]
0
R/W
20H
Revision ID
REVISION_ID
[7:0]
0
R/O
1000H MAC & I/O Control Module of Port 0
00H
configurable preamble bytes
PREAM_CFG
[2:0]
7
R/W
01H
configurable frame gap in di bits for 1st interval IFG_CFG
[5:0]
32
R/W
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