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VIA Technologies, Inc.
Preliminary VT6508 Datasheet
99/12/09
9
BLOCK DIAGRAM
EEPROM
Control
(eeprom init)
Serial
EEPROM
interface
PHY Control
(auto polling)
MII
management
interface
8-bit
IDE bus
Output
Control
Ethernet
TMAC
Buffer Control
(fully bit-map
management)
Input
Control
Input Control
RMAC
Ethernet
RMAC
Scheduler
LED
Serial-Out
Control
LED
serial-out
bus
Forwarding
Table Control
(drop control)
Queue
Control
(flow control)
CPU IO
Control
CPU Interface
RMII interface x 8
32-bit SRAM bus
RMII2MII
Translator
MII
interface
SRAM
Control
VT6508
Figure 1: Function Block Diagram of VT6508. (Note that some interface signals are only
available in VT6509 of 208-pin PQFP package.)