
VIA Technologies, Inc.
Preliminary VT6508 Datasheet
-38-
02H
EEPROM device address
bit 7-4 : device type id (default as1010)
bit 3-1 : device id
bit 0 : r/w command
à
value 0: write; value 1: read
EEDEVADDR
[7:0]
R/W
03H
EEPROM status register
EESTS[0]: value 0: idle, 1: busy (r/w or auto-init
in progress)
EESTS[1]: value 1: r/w complete without error
(cleared by register read)
EESTS[2]: value 1: r/w ack error
EESTS[3]: value 0: no init error, 1: init err
EESTS
[3:0]
R/O
0600H CPU interface
00H
interrupt status/clear register
bit 0: PHY command complete interrupt
bit 1: EEPROM command interrupt
bit 2: PHY auto-polling link status change
notification
bit 3: EEPROM initialization complete interrupt
bit 4: interrupt indication for CPU IO port
receiving an incoming packet from some
Ethernet port, that is ready to be received
by CPU via IDE.
bit 5: interrupt indication for CPU IO port finishing
the transmission of an outgoing packet that
was sent by CPU via IDE.
bit 6: interrupt indication for re-autonegotiation
caused by port speed mismatch
Note that writing 1 to the corresponding register
bits will clear that interrupts.
IRQSTS
[5:0]
[6:0]
0
R/W
01H
interrupt mask register
bit 0: PHY command complete interrupt mask
bit 1: EEPROM command interrupt mask
bit 2: PHY auto-polling link status change
notification mask
bit 3: EEPROM initialization complete interrupt
mask
bit 4: interrupt mask for CPU IO port
receiving an incoming packet from some
Ethernet port, that is ready to be received
by CPU via IDE.
bit 5: interrupt mask for CPU IO port finishing
the transmission of an outgoing packet that
was sent by CPU via IDE.
bit 6: interrupt indication for re-autonegotiation
caused by port speed mismatch
Note: value 0 means “ masked” , value 1 means
“ not masked” . The default is “ masked” so that
software has to poll IRQSTS to check if there are
any pending interrupts.
IRQMASK
[5:0]
[6:0]
0
R/W