VIA Technologies, Inc.
Preliminary VT6508 Datasheet
-14-
SD[24]
Hash Algorithm Selection:
HASH_ALG_SEL == 1 => CRC-map with scramble (default)
HASH_ALG_SEL == 0 => Direct-map without scramble
HASH_ALG_SEL == 1 will make the register HASH_ALG[1:0]=0 that is helpful to the
X-Stream test.
HASH_ALG_SEL == 0 will make the register HASH_ALG[1:0]=3 that can get a good
result of 4094 MAC addresses in Address Handling test.
SD[25]
No Swap EEPROM and LED output pins:
NO_SWAP_EEPROM_LED == 1 => The pins 192/193 are used as
EEIO/EEC. (default)
NO_SWAP_EEPROM_LED == 0 => The pins 192/193 are used as
LEDIO/LEDC.
In 128-pin package, we can bond this pin to VSS to select LED output from the original
EEPROM output pins.
SD[26]
Enable Aging:
EN_AGING == 1 => enable aging function (default)
EN_AGING == 0 => disable aging function
SD[27]
Disable Cut Through Enable:
DIS_CUT_THRU == 1 => disable cut-through feature
(default, i.e. store & forward)
DIS_CUT_THRU == 0 => enable cut-through feature
SD[28]
Disable Aggressive Backoff Algorithm:
DIS_AGGRES_BACKOFF == 1’ b1 => disabled (default)
DIS_AGGRES_BACKOFF == 1’ b0 => enabled
Note that if this feature is enabled, the backoff algorithm for all Ethernet ports is in MBA
mode. By default, the backoff algorithm bits MBA=0 and OFSET=1.
SD[29]
Backpreasure Collision Point Configuration:
COLL_POINT_CFG == 1 => 32th byte (default)
COLL_POINT_CFG == 0 => 2nd byte
SD[30]
Disable TEST mode:
DIS_TEST_MODE == 1 => disabled (default)
DIS_TEST_MODE == 1 => enabled
SD[31]
Disable Latchup Mode:
DIS_LATCH_UP_MODE == 1’ b1 => disable Latchup mode (default)
DIS_LATCH_UP_MODE == 1’ b0 => enable Latchup mode, all output only IO PADs
are in tri-state after reset.
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