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VT6508 Datasheet(PDF) 42 Page - List of Unclassifed Manufacturers

Part # VT6508
Description  8 RMII PORTS OF 10/100BASE-T/TX ETHERNET SWITCH CONTROLLER
PDF  48 Pages
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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VT6508 Datasheet(HTML) 42 Page - List of Unclassifed Manufacturers

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VIA Technologies, Inc.
Preliminary VT6508 Datasheet
-42-
05-06H Granted 1
st free buffer Addr in Input Control
bit [10:0]: buffer address (ID*3 + 40h)
bit [11]: buffer address valid (default: invalid)
bit [12]: buffer free (available for the new
incoming packet)
FREE_BUF_ADDR1 [12:0]
0
R/O
07-08H Granted 2
nd free buffer Addr in Input Control
bit [10:0]: buffer address (ID*3 + 40h)
bit [11]: buffer address valid (default: invalid)
bit [12]: buffer free (available for the new
incoming packet)
FREE_BUF_ADDR2 [12:0]
0
R/O
09-0AH Event mask for counters
EVENT_MASK[0]: rx CRC good packets
for Counter 1
EVENT_MASK[1]: rx flow control frames for
Counter 1
--------------------------------------------------------------
-
EVENT_MASK[2]: rx a runt packet for Counter 2
EVENT_MASK[3]: rx an over-size packet for
Counter 2
EVENT_MASK[4]: rx a regular-size but CRC
error packet for Counter 2
--------------------------------------------------------------
-
EVENT_MASK[5]: FIFO over-run without buffer
starvation for Counter 3
EVENT_MASK[6]: FIFO over-run with buffer
starvation for Counter 3
EVENT_MASK[7]: intended drop local packets
for Counter 3
EVENT_MASK[8]: drop broadcast packets due
to congestion for Counter 3
EVENT_MASK[9]: drop unicast packets due
to congestion for Counter 3
--------------------------------------------------------------
-
EVENT_MASK[10]: tx packets excluding flow
control packets for counter 4
EVENT_MASK[11]: tx flow control packets for
counter 4
--------------------------------------------------------------
-
EVENT_MASK[12]: FIFO under-run for
Counter 5
EVENT_MASK[13]: collision for Counter 5
EVENT_MASK[14]: first 16-bit packet data late
(can not catch up preamble)
for counter 5
EVENT_MASK
[14:0]
7FFF
R/W
10H-
11H
received good packet count (Counter 1)
It is cleared automatically after CPU read.
RCV_GOOD_PKT
[15:0]
0
R/O
12H-
13H
received bad packet count (Counter 2)
It is cleared automatically after CPU read.
RCV_BAD_PKT
[15:0]
0
R/O
14H-
15H
drop packet counter(Counter 3)
It is cleared automatically after CPU read.
DROP_PKT
[15:0]
0
R/O



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