VIA Technologies, Inc.
Preliminary VT6508 Datasheet
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TABLE OF CONTENTS
TABLE OF CONTENTS ................................................................................................................................ 3
FIGURES AND TABLES ............................................................................................................................... 4
REVERSION HISTORY ................................................................................................................................ 5
FEATURES ................................................................................................................................................ 6
BLOCK DIAGRAM...................................................................................................................................... 9
FIGURE 1: FUNCTION BLOCK DIAGRAM OF VT6508. (NOTE THAT SOME INTERFACE
SIGNALS ARE ONLY AVAILABLE IN VT6509 OF 208-PIN PQFP PACKAGE.).............................. 9
PINOUT DIAGRAM................................................................................................................................... 10
FIGURE 2: PINOUT DIAGRAM OF VT6508. ...................................................................................... 10
PIN DESCRIPTIONS .................................................................................................................................. 11
DEFINITION OF VT6508B STRAPPING PINS .............................................................................................. 12
Pin.................................................................................................................................................... 12
SRAM TYPE: .................................................................................................................................... 12
SECTION I FUNCTIONAL DESCRIPTIONS...................................................................................... 15
1 GENERAL DESCRIPTION ...................................................................................................................... 15
2 THE VIA ETHER SWITCH ARCHITECTURE............................................................................................ 15
2.1 Switch initialization procedures .................................................................................................. 15
2.2 Packet Switching Flow ................................................................................................................ 16
2.3 PACKET BUFFERS AND FORWARDING TABLE ...................................................................................... 16
FIGURE 3. SRAM MEMORY LAYOUT............................................................................................... 17
FIGURE 4. DATA STRUCTURE OF FORWARDING TABLE SLOT................................................ 17
FIGURE 5. DATA STRUCTURE OF EMBEDDED LINK NODE. ...................................................... 17
2.3 RMII INTERFACE.............................................................................................................................. 19
2.3 MANAGEMENT INTERFACE AND AUTO NEGOTIATION ......................................................................... 19
2.4 FLOW CONTROL ............................................................................................................................... 21
FIGURE 6. XON/XOFF WINDOW CONCEPT..................................................................................... 23
2.5 BROADCAST STORM FILTERING ......................................................................................................... 27
2.6 SERIAL EEPROM INTERFACE AND CONFIGURATION COMMANDS ........................................................ 27
2.7 TRUNKING....................................................................................................................................... 28
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THE VT6508 SRAM ADDRESS MAPPING TABLE ............................................................... 30
SECTION II REGISTER MAP............................................................................................................... 31
1. REGISTERS TABLE ............................................................................................................................. 31
SECTION III ELECTRICAL SPECIFICATIONS................................................................................. 45
ABSOLUTE MAXIMUM RATINGS............................................................................................................... 45
DC CHARACTERISTICS............................................................................................................................ 45
AC CHARACTERISTICS............................................................................................................................ 46
PACKAGE MECHANICAL SPECIFICATIONS ................................................................................................. 48
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