VT6508 datasheet(37/48 Pages) ETC1

37 / 48 page

VIA Technologies, Inc.

Preliminary VT6508 Datasheet

-37-

02-03H CPU command R/W data

The last data word read from PHY is stored in this

Note that the last data word written to PHY is

stored in an internal register that is also located in

this address for CPU write, but not readable.

PHYDATA

[15:0]

R/W

04H

CPU command register

PHYCMD[3]: enable phy auto-polling

PHYCMD[2]: disable phy auto-polling

PHYCMD[1]: phy read command.

PHYCMD[0]: phy write command.

When auto-polling mechanism is enabled, CPU

can not read/write PHY devices, even though the

PHY (auto-polling) Debug Mode is enabled.

PHYCMD

[3:0]

W/O

R/W

05H

PHY status register

Bit-0: 0=cmd_idle; 1=cmd_busy

Bit-1: 0=cmd_incomplete; 1=cmd_complete

Bit-2: 0=autopoll_off; 1=autopoll_on

Note that the “ cmd” means the command from

CPU interface, not from auto-polling control.

PHYSTS

[2:0]

R/O

06-07H Link status change

1’ b1=link status changed

1’ b0=link status without changed

(cleared after cpu read)

LINK_STATUS_CHA

NGE

[8:0]

R/O

08-09H Link status

1’ b0=link down (default)

1’ b1=link up

LINK_STATUS

[8:0]

R/O

R/W

0AH

PHY debug mode enable

PHY_DBG_EN: enable debug auto-polling state

Machine for validation

Value 1: enabled

Value 0: disabled

PHY_DBG_EN

[0]

R/W

0BH

Trigger Auto-Polling Single Step

Write value 1 to trigger a single step, then this bit

is self-cleared after command complete.

This operation may takes about 30 s.

TRIG_STEP_POLL

[0]

R/W

10-18H PHY Device Address

PHY_ADDR

[4:0]

R/W

0500H

EEPROM control

00H

EEPROM word address

For a 256-byte EEPROM device, an 8-bit data

object is identified with this register. For a 512-

byte EEPROM device, an 8-bit data object is

identified with this register plus EEDEVADDR[1],

vice versa.

EEWDADDR

[7:0]

R/W

01H

EEPROM data

The last data byte read from EEPROM is stored

in this register for CPU read.

Note that the last data byte written to EEPROM is

stored in an internal register that is also located in

this address for CPU write, but not readable.

EEDATA

[7:0]

R/W

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