VIA Technologies, Inc.
Preliminary VT6508 Datasheet
-43-
16H-
17H
sent good packet count(Counter 4)
It is cleared automatically after CPU read.
XMT_GOOD_PKT
[15:0]
0
R/O
18H-
19H
sent bad packet counter(Counter 5)
It is cleared automatically after CPU read.
XMT_BAD_PKT
[15:0]
0
R/O
1AH-
1BH
sent abort packet counter(Counter 6)
(abort due to excessive transmission fails)
It is cleared automatically after CPU read.
XMT_ABORT_PKT
[15:0]
0
R/O
1C-
1DH
dequeued 1
st buffer Addr in Output Control
bit [10:0]: buffer address (ID*3 + 40h)
bit [11]: buffer address valid (default: invalid)
DEQUEUED_BUF_A
DDR1
[11:0]
0
R/O
1E-
1FH
dequeued 2
nd buffer Addr in Output Control
bit [10:0]: buffer address (ID*3 + 40h)
bit [11]: buffer address valid (default: invalid)
DEQUEUED_BUF_A
DDR2
[11:0]
0
R/O
20H
Internal state of Input Control
(reserved for Weipin’ s definition)
(only valid for port 0)
INPUT_CTL_STATE [7:0]
0
R/O
21H
Internal state of Output Control
(reserved for Weipin’ s definition)
(only valid for port 0)
OUTPUT_CTL_STA
TE
[7:0]
0
R/O
1100H MAC & I/O Control Module of Port 1
same as Port 0
1200H MAC & I/O Control Module of Port 2
same as Port 0
1300H MAC & I/O Control Module of Port 3
same as Port 0
1400H MAC & I/O Control Module of Port 4
same as Port 0
1500H MAC & I/O Control Module of Port 5
same as Port 0
1600H MAC & I/O Control Module of Port 6
same as Port 0
1700H MAC & I/O Control Module of Port 7
same as Port 0
1800H MAC & I/O Control Module of Port 8
same as Port 0
1900H CPU I/O Control Module
00H
CPU packet read byte count register bits [7:0]
CPU can check the incoming (ready to be
received by CPU via IDE) packet length via the
11-bit register PKT_BYTE_CNT [10:0] before
starting to read it.
PKT_BYTE_CNT
[7:0]
0
R/O
01H
CPU packet read byte count register bits
[10:8]
PKT_BYTE_CNT
[10:8]
0
R/O
02H
CPU packet read status register
2’ b00: idle or packet read (by CPU) in progress
2’ b01: packet read (by CPU) complete without
error
2’ b10: packet read (by CPU) with error
(CPU needs to read the same packet again)
RD_PKT_STATUS
[1:0]
0
R/O
03H
Packet source port ID
CPU can check the incoming packet’ s source
port ID via the 3-bit register PKT_SRC_PORT
before starting to read it. It is useful to the
spanning tree algorithm.
PKT_SRC_PORT
[3:0]
0
R/O
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