VIA Technologies, Inc.
Preliminary VT6508 Datasheet
-16-
2.2 Packet Switching Flow
1. After initialization, the input control of each enabled port will pre-allocate one packet
buffer from the free buffer pool.
2. When the Receive MAC (RMAC) receives a packet data from the PHY device via the
RMII network interface, it packs the data into 16-bit words then passes it to input control.
If RMAC detects any error, it also notifies input control to stop forwarding process.
3. Input control extracts the destination MAC address from incoming data, passes it to
forwarding table control for forwarding decision. In the mean while, it packs 16-bit words
into 64-bit quad-words, and saves it to an input FIFO before storing the packet data to
packet buffers in SRAM.
4. If the switch is configured to “store and forward” mode, input control queues the packet to
the output queue of the destination port after input control is informed by RMAC that this
is a good packet and it stores all packet data to SRAM. If the switch is configured to
“cut-through” mode, the input control queues the packet to the output queue of the
destination port after the first 64-byte packet data is stored in SRAM to prevent output
FIFO underrun.
5. After the whole packet is received and FCS is correct, input control pass the source MAC
address of the packet to forwarding table control for address learning.
6. Output control of the outbound port dequeues the packet from itself output queue, and
fetches packet data from SRAM and saves it into output FIFO. Then it notifies the
Transmit MAC (TMAC) to transmit the read-to-outgoing packet.
7. TMAC grabs 16-bit word at a time from output control, adds preamble and SFD to the
beginning of the packet, then send them out. Proper deferring is done for collision to
conform to 802.3 standard.
8. After the packet is successfully transmitted, TMAC notifies output control of the
successful transmission. Output control then returns the packet to the free buffer pool.
2.3 PACKET BUFFERS AND FORWARDING TABLE
VT6508 provides a 32-bit SRAM interface for packet buffering and maintaining address table
and per-port output link lists. Each packet buffer is a 1536-byte contiguous memory block in
SRAM, and it also contains to a 8-byte link node data structure in every buffer’s tail. A link
node corresponds uniquely to a packet buffer that could belong an output queue, the free
buffer pool, incoming packet buffers of an input control, or outgoing packet buffers of an
output control.
Initially, each input port control will request one packet buffer from its private buffer pool.
Each time when a packet buffer is consumed by an incoming packet, the input port control will
request another packet buffer to prepare for next packet.
There are two data structures in SRAM memory layout, shown in Figure 3. One is the
forwarding table that locates at the lowest 32K-byte address space and contains 2048 entries
(buckets), each of 2 slots. The structure of an 64-bit forwarding table slot is shown in Figure 4,
composed of:
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