VIA Technologies, Inc.
Preliminary VT6508 Datasheet
-44-
04H
CPU IO port configuration register
bit 0 : input port enable
à 1: input enable, 0: input
disable
bit 1 : output port enable
à 1: output enable, 0:
output disable
bit 2 : output port dequeue hold
à 1: dequeue
disabled, 0: dequeue enabled
Note that the broadcast domain is determined by
the CPUIO_CFG[1] and 9 bits of all Ethernet
ports’ IO_CFG[1]. If CPUIO_CFG[1]==0, the
CPU port must be not within the broadcast
domain.
CPUIO_CFG
[2:0]
0
R/W
05-06H
Granted (at most one) free buffer Addr in
Input Control
Bit [10:0]: buffer address (ID*3 + 40h)
Bit [11]: buffer address valid
FREE_BUF_ADDR
[11:0]
0
R/O
07-08H
dequeued buffer Addr in Output Control
bit [10:0]: buffer address (ID*3 + 40h)
bit [11]: buffer address valid (default: invalid)
DEQUEUED_BUF_A
DDR
[11:0]
0
R/O
10H
CPU packet write status register
bits [1:0] : packet write status
2’ b00: idle or packet write in progress
2’ b01: CPU sent packet successfully
2’ b10: CPU sent packet unsuccessfully
(CPU needs to re-write the
packet again)
Note that CPU packets have highest priority and
will not be dropped by Forwarding Control.
bit 2: CPU Input Control is ready for CPU to write
packets (It can be ready only after setting
CPUIO_CFG[0] = 1.)
0: not ready (default)
1: ready
Note that if CPU IO is in XOFF window, it will be
not ready with WR_PKT_STATUS[2]==1. CPU
IO always uses flow control mechanism with
displaying XON/XOFF status in
XOFF_WINDOW[9] of Forwarding Control.
WR_PKT_STATUS
[2:0]
0
R/O
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