
VIA Technologies, Inc.
Preliminary VT6508 Datasheet
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step2. Check the chip internal register, phyint_setup_reg, to setup the pause capability
(Reg4.10) and phy auto-negotiation enable (Reg0.12)
- if (this port do not need phy setup) and (phyint_setup_reg == done),
then go to step 10(done)
- else if (this port do not need phy setup) and (phyint_setup_reg != done),
then config ioctl, set phyint_setup_reg == done, go to step10(done)
- else if (phyint_setup_reg != done),
then go to step3(phy fc setup)
- else if (this port do not need auto-poll,
then go to step 10(done)
- else go to step 5(read phy link status)
step3. Phy flow_control ability setup
- if the phy_pause_ability(reg4.10) != port_phy_fc_set,
then write reg4.10 = port_phy_fc_set and go to step4 (phy auto-negotiation ability
setup)
- else go to step4 (phy auto-negotiation ability setup)
step4. PHY auto-negotiation ability setup
- if (Reg0.12)=”1”(on), then modify chip internal register for phyint_setup_reg = done;
go to step5
- else if (Reg0.12)=”0”(off) or phy_pause_ability have been modified ( in step3 ), then
write PHY auto-negotiation_enable bit (Reg0.12) =”1” (on), restart_auto-negotiation
bit (Reg0.9) = “1” and modify chip internal register for phyint_setup_reg = done; go to
step5
step5. Read PHY link_status bit (Reg1.2) 1
st time
- if link is down (Reg1.2)=”0”, then go to step6
- else if link is up (Reg1.2)=”1” and chip_internal_reg for link status is “down”, then go to
step7
- else if link is up (Reg1.2)=”1” and chip_internal_reg for link status is “up”, then go to
step10.
step6. Read PHY link_status bit (Reg1.2) 2
st time
- if link is up (Reg1.2)=”1”, then go to step7
- else if link is down (Reg1.2)=”0”, then go to step10
*if chip_internal_reg for link status is “down”=> generate link_change
interrupt and disable io_port
step7. Read PHY Auto-negotiation Complete bit (Reg1.5)
- if auto-negotiation is completed (Reg1.5)=”1”, then go to step8.
- else if auto-negotiation is not completed (Reg1.5)=”0”, then go to step10.