Electronic Components Datasheet Search
  English  ▼

X  

CS43198 Datasheet(PDF) 39 Page - Cirrus Logic

Part # CS43198
Description  130-dB, 32-Bit High-Performance DAC with Pseudodifferential Outputs
PDF  137 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43198 Datasheet(HTML) 39 Page - Cirrus Logic

Back Button CS43198 Datasheet HTML 35Page - Cirrus Logic CS43198 Datasheet HTML 36Page - Cirrus Logic CS43198 Datasheet HTML 37Page - Cirrus Logic CS43198 Datasheet HTML 38Page - Cirrus Logic CS43198 Datasheet HTML 39Page - Cirrus Logic CS43198 Datasheet HTML 40Page - Cirrus Logic CS43198 Datasheet HTML 41Page - Cirrus Logic CS43198 Datasheet HTML 42Page - Cirrus Logic CS43198 Datasheet HTML 43Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 39 / 137 page
background image
DS1156F1
39
CS43198
4.7 Filtering Options
7. After properly unmasked (clearing PLL_READY_INT_MASK and PLL_ERROR_INT_MASK), PLL_READY_INT,
and PLL_ERROR_INT are used to monitor if PLL has been successfully started.
8. Turn on the PLL by setting PLL_START.
4.6.2.2 Powering Down the PLL
1. Clear PLL_START to stop the PLL operation.
2. For further power saving, set PDN_PLL to disable the PLL block.
4.7 Filtering Options
To accommodate the increasingly complex requirements of digital audio systems, the CS43198 incorporates selectable
filters in different playback modes.
For PCM/TDM mode, the following interpolation filtering options can be selected:
• Fast roll-off and slow roll-off interpolation filter options.
• In each option above, both low-latency and normal phase-compensation filtering options can be used.
• Nonoversampling (NOS) mode is provided, which minimizes the internal digital processing. Once NOS mode is set,
the settings on the above two options are ignored.
The combination of the options results in five different filter combinations. The specifications for each filter can be found
in Table 3-7, and response plots can be found in Section 9. These filters have been designed to accommodate a variety
of musical tastes and styles. The PCM filter option register (see Section 7.5.2) is used to select filter options.
When in octuple-speed mode, the filter options above are not available and the internal digital processing is minimized.
See the specification in Table 3-7 for filter characteristics.
The DSD processor mode uses a decimation-free DSD processing technique that allows for features such as matched
PCM level output, DSD volume control, and 50-kHz on-chip filter.
In Direct DSD Mode, the DSD stream directly controls the DAC elements for minimal processing. Since there is no 50-kHz
on-chip filter in the signal path, external filter designs must be compliant with SACD requirements.
4.8 Audio Serial Port (ASP)
The independent, highly configurable ASPs and auxiliary serial ports (XSPs) communicate audio data from other system
devices, such as applications processors. Both ports can be configured to support common audio interfaces, TDM/I2S and
left-justified (LJ).
ASP supports both PCM and DoP stream playback. XSP can only support DoP stream playback. For DAC playback, only
one port needs to be enabled. Both ports are enabled only in specific application, such as PCM notification mixing with
DSD/DoP content. Details regarding this application setup can be found in Section 4.11.
In this section, the reference to both ports is generalized as “xSP” to explain the common settings between the two ports.
4.8.1
Master and Slave Timing
Each serial port can operate as either the master of timing or as a slave to another device’s timing. If xSP_M/S is set, the
serial port acts as a clock master. If xSP_M/S is cleared, the serial port acts as a clock slave.
• In Master Mode, xSP_SCLK and xSP_LRCK are outputs derived from the internal MCLK.
• In Slave Mode, xSP_SCLK and xSP_LRCK are inputs. Although the CS43198 does not generate the interface
timings in Slave Mode, the expected LRCK and SCLK format must be programmed in the same way as in Master
Mode (see Table 3-18).
• In both modes, the serial port sample rate register (xSP_SPRATE) must be set per audio content before enabling
the serial port.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com