CS43198 datasheet(21/137 Pages) CIRRUS

21 / 137 page

DS1156F1

CS43198

3 Characteristics and Specifications

1.PSRR test configuration: Typical PSRR can vary by approximately 6 dB below

the indicated values.

Table 3-16. DC Characteristics

Test conditions (unless otherwise specified): Fig. 2-1 shows CS43198 connections; GNDD = GNDA = 0 V; all voltages with respect to ground.

Parameters

Minimum

Typical

Maximum Units

VCP_FILT (No load connected to AOUTx)

EXT_VCPFILT = 0

VP_LDO Mode

VCP_FILT+ pin (HV_EN = 1)

VCP_FILT+ pin (HV_EN = 0)

VCP_FILT– pin (HV_EN = 1)

VCP_FILT– pin (HV_EN = 0)

—

3.0

2.6

–3.0

–2.6

—

VCP Mode

VCP_FILT+ pin

VCP_FILT– pin

—

VCP

–VCP

—

–VA

–VA pin

—

– VA

—

Other DC characteristics

FILT+ voltage

—

–0.35

—

FILT– voltage

—

0.35

—

Analog output current limiter on threshold.

—

120

160

VD power-on

reset threshold

(VPOR)

Down

—

1.15

0.950

—

Table 3-17. Power Consumption

Test conditions (unless specified otherwise): Fig. 2-1 shows CS43198 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;

performance data taken with VA = VCP = VD = VL = 1.8 V; VP = 3.6 V; TA = +25°C; ASP_SPRATE = 0001(44.1-kHz mode); MCLK_INT= 1

(22.5792 MHz); MCLK_SRC_SEL = 00; +1dB_EN = 1; all other fields are set to defaults; no signal on any input; control port inactive; all serial ports are

set to Slave or Master Mode as indicated, input clock/data are held low unless active; test load is RL = 600  and CL = 1 nF for AOUTx; measured values

include currents consumed by the DAC and do not include current delivered to external loads unless specified otherwise (e.g., from AOUTx outputs); see

Fig. 2-1.

Use Cases

Typical Current (µA)

Total

Power

(µW)

POUT

iVCP

iVA

iVD

iVL

iVP

1Off 1

1.Off configuration: Clock/data lines held low; RESET = LOW; VA = VD = VL = 0 V, VCP = 0 V, VP = 3.6 V.

—0

Standby 2

2.Standby configuration: Clock/data lines held low; RESET = HIGH; VA = VD = VL = 1.8 V, VCP = 1.8 V, VP = 3.6 V; HP_DETECT_CTRL = 11 (enabled);

HPDETECT_PLUG_INT_MASK=0 (unmasked); PDN_XTAL = 1, MCLK_SRC_SEL = 10 (RCO selected as MCLK source).

HPDETECT enabled

—

256

576

3 A Playback

External MCLK = 22.5792 MHz, I2S/DoP

Stereo AOUT

Quiescent 3

3.Quiescent configuration: data lines held low; RESET = HIGH; VA = 1.8 V, VD = VL = VCP = 1.8 V, VP = 3.6 V. Serial port, I2S/DoP Mode (ASP and

SDIN, ASP_M/Sb = 0); PDN_XTAL = 1.

3808

7835

2786

26074

Table 3-18. Serial-Port Interface Characteristics

Test conditions (unless specified otherwise): Fig. 2-1 shows CS43198 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;

parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL =

1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; TA = +25°C; CL = 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at VOL and VOH thresholds

(see Table 3-11).

Parameters 1,2,3,4

Symbol

Minimum

Typical

Maximum

Units

FSYNC frame rate

(See

Section 4.8.5)

kHz

FSYNC high period 5

tHI:FSYNC

1/fSCLK

—

(n–1)/fSCLK

Operational Amplifier

OUT

GND

Power DAC

OUT

GND

PWR

DUT

+5 V

+–

–

OUT

Analog Generator

Analog Analyzer

Analog Test Equipment

Analog Output PSRR

CS43198 Datasheet(PDF) 21 Page - Cirrus Logic

CS43198 Datasheet(HTML) 21 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL