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CS43198 Datasheet(PDF) 82 Page - Cirrus Logic |
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CS43198 Datasheet(HTML) 82 Page - Cirrus Logic |
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82 / 137 page  82 DS1156F1 CS43198 5.12 Example Sequences 5.12.7 Switching MCLK Frequency Ex. 5-11 shows steps necessary to switch the MCLK frequency in order to play audio at a different sample rate that is no longer an integer divide of current MCLK. It makes the following assumptions: • The CS43198 is already powered up and out of reset. • MCLK_INT is 22.5792 MHz, and the sample rate is an integer divide of MCLK. • ASP is used for audio delivery and PDN_HP = 0. 5.12.8 Headphone Detection Ex. 5-12 shows steps necessary to detect the presence of a headphone. It makes the following assumptions: • The CS43198 is already powered up and out of reset. • The HP Detect register is not configured. Example 5-11. Sequence for Switching MCLK Frequency STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION 1 Power down PCM Refer to Ex. 5-1 for PCM power-down sequence 2 Switch MCLK Source to RCO 3 Set MCLK Source to RCO System Clocking Control 1. 0x10006 0x06 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 1 10 Frequency of MCLK_INT is don't care MCLK source set to RCO 4 Wait for 150 µs. 5 Switch to a different MCLK Frequency. Assuming new MCLK frequency is 24.576MHz. 6 Change MCLK_INT frequency to 24.576 MHz System Clocking Control 1. 0x10006 0x02 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 0 10 MCLK_INT frequency set to 24.576 MHz 7 Configure ASP for appropriate sample rate, bit size and clock mode. Unmute PCM CHA and CHB outputs. Enable appropriate interrupts 8 Switch MCLK source to direct MCLK mode System Clocking Control 1. 0x10006 0x0 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 0 00 MCLK_INT frequency set to 24.576 MHz MCLK source set to direct MCLK mode 9 Wait at least 150 µs. 10 Power up ASP Power Down Control. 0x20000 data(0x20000) AND (0xBF) PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x 0 x 1 0 x x 0 Enable ASP data pins XTAL is already enabled 11 Power up DAC Refer to Ex. 5-3 for PCM power-up sequence Example 5-12. Sequence for Headphone Detection STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION 1 Read Interrupt Status 1 register (0xF0000) to clear any sticky bits. 2 Read HP Status register (0xD0001) to clear any sticky bits. 3 Enable HPDETECT interrupts Interrupt Mask 1. 0xF0010 data (0xF0010) AND 0x9F DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK x 0 0 x x x x x Enable HPDETECT interrupts 4 Configure HP Detect parameters HP Detect. 0xD0000 0x04 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved 00 0 0 0 10 0 Rising edge debounce time set to 0 ms Falling edge debounce time set to 500 ms |
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