CS43198 datasheet(27/137 Pages) CIRRUS

27 / 137 page

DS1156F1

CS43198

4.2 Analog Outputs

The CS43198 provides an analog output that is derived from the digital audio input ports. This section describes the

general flow of the analog outputs.

4.2.1

Analog Output Signal Flow

The CS43198 signal flow is shown in Fig. 4-1.

Figure 4-1. Analog Output Signal Flow

The CS43198 has 4 settings of full scale voltage, which are determined by OUT_FS[1:0]. When OUT_FS[1:0] = 11 and

HV_EN = 1, the +1dB_EN bit can boost the output voltage to 2 Vrms. In any other setting combination of OUT_FS[1:0] and

HV_EN, the +1dB_EN bit is ignored. The proper full scale voltage must be set first, and the digital volume settings is used

to control signal levels.

The CS43198 digital volume control allows independent control of the signal level in 1/2 dB increments from 0 dB

(0b0000 0000) to –127 dB (0b1111 1110) by using x_VOLUME_y (where "x" is either PCM or DSD; "y" is either A or B)

volume changes are implemented as dictated by PCM_SZC[1:0] and DSD_SZC in the signal control register (see

Section 7.4.3 and Section 7.5.5). If soft ramping is enabled, gain and attenuation changes are carried out by incrementally

changing the volume level in 1/8-dB steps, from the previous level to the new level. For PCM, when PCM_SZC[1:0] = 2,

the volume level changes at an approximate rate of 1 dB/ms. The volume level also changes at a rate of 1 dB/ms for DSD.

Both channels can be inverted independently by setting the INV_A and INV_B bits. Both channels can be swapped by

setting the x_SWAP_CHAN bit. Channel A content can be copied to channel B by setting the x_COPY_CHAN bit. Mono

mode can be enabled with proper setting of these bits.

The CS43198 provides individual ramp-up and ramp-down control options (from the global soft ramp settings) for two

specific scenarios. The PCM_RAMP_DOWN bit is for the scenario when the interpolation filter configuration switches (as

configured by the PCM Filter Option register) during PCM playback. DSD_RAMP_UP bit is for the scenario when DSD

playback recovers from detected DSD stream errors. Refer to each individual register description for setting details.

The CS43198 can mute both channels simultaneously or independently. Also, it can auto-mute on both PCM stream and

DSD stream when mute pattern is identified (defined in PCM_AMUTE and DSD_AMUTE). Additional signal and mute

control options can be found in Section 7.4.3 and Section 7.5.5.

Multibit



Modulator

Multibit



Modulator

Interpolation

Filter &

Volume

Control

Interpolation

Filter &

Volume

Control

AOUTA

AOUTB

DSD

Processor

DoP to

DSD

Engine

Audio

Source

I2S

REFB

REFA

DoP

DSD



DAC and

Filter

DAC and

Filter

DAC_OVFL_INT p. 115

DSD_PRC_SRC p. 109

DIR_DSD p. 109

DSD_DIRECT_MC p. 110

DSD_DIRECT_GAIN p. 110

PCM_SZC p. 112

DSD_RAMP_UP p. 108

PCM_RAMP_DOWN p. 112

PCM_VOLUME_B p. 112

PCM_VOLUME_A p. 112

PCM_INV_A p. 113

PCM_INV_B p. 113

PCM_SWAP_CHAN p. 113

PCM_COPY_CHAN p. 113

PCM_VOL_BEQA p. 112

PCM_AMUTE p. 112

PCM_AMUTEBEQA p. 112

PCM_MUTE_A p. 112

PCM_MUTE_B p. 112

FILTER_SLOW_FASTB

p. 111

PHCOMP_LOWLATB p. 111

HIGH_PASS p. 111

DEEMP_ON p. 111

MIX_PCM_PREP p. 109

MIX_PCM_DSD p. 109

+1dB_EN p. 111

OUT_FS p. 111

PCM_WBF_EN p. 111

DSD_EN p. 109

DSD_SPEED p. 109

STA_DSD_DET p. 109

INV_DSD_DET p. 109

DSD_VOLUME_B p. 107

DSD_VOLUME_A p. 108

DSD_INV_A p. 110

DSD_INV_B p. 110

DSD_VOL_BEQA p. 108

DSD_AMUTE p. 108

DSD_MUTE_A p. 108

DSD_MUTE_B p. 108

DSD_ZERODB p. 110

DSD_HPF_EN p. 110

OUT_FS p. 111

DSD_SZC p. 108

DSD_RAMP_UP p. 108

DSD_SWAP_CHAN p. 110

DSD_COPY_CHAN p. 110

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