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CS43198 Datasheet(PDF) 52 Page - Cirrus Logic

Part # CS43198
Description  130-dB, 32-Bit High-Performance DAC with Pseudodifferential Outputs
PDF  137 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43198 Datasheet(HTML) 52 Page - Cirrus Logic

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52
DS1156F1
CS43198
4.12 Control Port Operation
To directly connect the ADR pin and ground, the last two bits of the I2C address are configured as the default 00. For the
other options, use a resistor (with 5% accuracy) as suggested in the Table 4-12.
If the operation is a write, the 3 bytes after the chip address are the memory address pointer (MAP) that select the address
of the register to be read or written to next. The byte following the MAP is the control byte. Bit[0] of the control byte, INCR,
selects whether autoincrementing is to be used (INCR = 1), allowing successive reads or writes of consecutive registers.
Bits[2:1] of the control byte indicate the size of the data for the autoincrement to be acted on. Table 4-13 explains the
format for the I2C control byte.
Each byte transferred on the I2C bus is separated by an acknowledge (ACK) bit. The CS43198 acknowledges each input
byte read from the host, and the host must acknowledge each byte transmitted from the CS43198.
For write operations, the data bytes following the MAP byte are written to the CS43198 register addresses pointed to by
the last received MAP address, plus however many autoincrements have occurred. Fig. 4-29 shows a write pattern with
autoincrementing.
Figure 4-29. Control Port Timing, I2C Writes with Autoincrement (8-bit Data Access)
Table 4-12. I2C Address Configurations
Connection Type
Resistor Value (
)
Last Two Bits of I2C Address
Pull-up to VL
0
11
Pull-up to VL
4990
10
Pull-down to GND
4990
01
Pull-down to GND
0
00 (Default)
Table 4-13. I2C Control-Byte Format
Bit
Name
Description
7:3
—
Reserved
Default: 0
2:1
SIZE
Register access width. Specifies the width of the register access.
00 8-bit (1 byte)
01–11 Reserved
0
INCR
Setting this bit allows the MAP address to autoincrement. The MAP address automatically increments every SIZE + 1 bytes
accessed consecutively.
0 Disabled
1 Enabled
SCL
CHIP ADDRESS
(WRITE)
MAP BYTE
High (23:16)
START
STOP
ACK
SDA
SDA
Source
Master
Master
Master
Pull-up
Slave
Slave
Pull-up
ACK
Slave
4
5
6 7 8
9
17 18
0
1
2
3
7 6 5 4 3 2 1 0
ACK
34
MAP BYTE
Mid (15:8)
MAP BYTE
Low (7:0)
36
ACK
ACK
CONTROL
BYTE
7 6 5 4 3 2 1 0
37 38
35
Empty
7
0
7
0
7
0
16
26 27
25
39 40 41 42 43 44
7
0
7
0
45
DATA
BYTE 1
DATA
BYTE N
Master
Master
Master
Master
M
Slave
Slave
Slave
Slave
MAP
ADDRESS
MAP
ADDRESS
+ (N–1)
ACK
ACK
Addr = 01100



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