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CS43198 Datasheet(PDF) 69 Page - Cirrus Logic |
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CS43198 Datasheet(HTML) 69 Page - Cirrus Logic |
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69 / 137 page  DS1156F1 69 CS43198 5.12 Example Sequences 23 Configure DSD path Signal Control 2 DSD Processor Path Signal Control 2. 0x70004 0x13 Reserved DSD_PRC_SRC DSD_EN Reserved DSD_SPEED STA_DSD_DET INV_DSD_DET 0 00 1 0 0 1 1 Set source of DSD processor to DSDIF Enable DSD playback Set DSD clock speed to 64•FS Static DSD detection enabled Invalid DSD detection enabled 24 Configure DAC output 25 Configure Class H Amplifier Class H Control. 0xB0000 0x1E Reserved ADPT_PWR HV_EN EXT_VCPFILT 000 111 1 0 Output signal determines voltage level High Voltage Mode Enabled Using Internal VCPFILT source. 26 Set DAC output to full scale Analog Output Control 1. 0x80000 0x30 Reserved Reserved OUT_FS Reserved Reserved Reserved +1dB_EN 0 0 11 0 0 0 0 Set DAC output to Full Scale (1.732 V rms) 27 Configure Headphone Detect HP Detect. 0xD0000 0x04 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved 00 0 00 10 0 HP detect disabled HP detect input is not inverted Tip Sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms 28 Headphone Detect HP Detect. 0xD0000 0xC4 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved 11 0 00 10 0 HP detect enabled HP detect input is not inverted Tip sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms 29 Enable Interrupts 30 Read Interrupt Status 1 register (0xF0000) and Interrupt Status 5 register (0xF0004) to clear sticky bits 31 Enable Headphone Detect Interrupts Interrupt Mask 1. 0xF0010 0x81 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK 1 0 0 0 0 0 0 1 Unmask HPDETECT_PLUG interrupt and HPDETECT_UNPLUG interrupt 32 Enable DSD Interrupts Interrupt Mask 5. 0xF0014 0x03 DSD_STUCK_INT_MASK DSD_INVAL_A_INT_MASK DSD_INVAL_B_INT_MASK DSD_SILENCE_A_INT_MASK DSD_SILENCE_B_INT_MASK DSD_RATE_ERROR_INT_MASK DOP_MRK_DET_INT_MASK DOP_ON_INT_MASK 0 0 0 0 0 0 1 1 Enable DSD_STUCK interrupt Enable DSD_INVAL_A interrupt Enable DSD_INVAL_B interrupt Enable DSD_SILENCE_A interrupt Enable DSD_SILENCE_B interrupt Enable DSD_RATE_ERROR interrupt Disable DOP_MRK_DET interrupt Disable DOP_ON interrupt 33 Wait for interrupt. Check if PLL_READY_INT = 1 in Interrupt Status 1 register(0xF0000) 34 Switch MCLK source to PLL System Clocking Control 1. 0x10006 0x01 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 0 01 MCLK Source set to PLL. MCLK_INT frequency set to 24.576 MHz 35 Wait at least 150 µs. 36 Power up DAC Refer to Ex. 5-4 for DSD power-up sequence. Note that in Step 1 of Ex. 5-4, use HH = DF for the DSD interface. Example 5-6. Startup to DSD Playback (Cont.) STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION |
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