CS43198 datasheet(28/137 Pages) CIRRUS

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DS1156F1

CS43198

4.3 Class H Output

The CS43198 has an independent set of controls for the DSD processor path as shown in Fig. 4-1. The DSD processor

also offers the control bit SIGCTL_DSDEQPCM, which maps the PCM_x setting to DSD_x setting, once enabled. As a

result, some of the DSD_x register settings are ignored. The registers affected are DSD_RAMP_UP, DSD_VOL_BEQA,

DSD_SZC, DSD_AMUTE, DSD_AMUTE_BEQA, DSD_MUTE_A, DSD_MUTE_B, DSD_INV_A, DSD_INV_B, DSD_

SWAP_CHAN, and DSD_COPY_CHAN. Refer to Section 7.4.1–Section 7.4.7 for control register details.

The CS43198 supports Direct DSD Mode up to a speed of 128•Fs. When enabled, DSD input data is sent directly to the

digital-to-analog conversion interface for a pure DSD conversion. In this mode, the full-scale DSD and PCM levels are not

matched, the dynamic range performance may be reduced, DC offset may be present in the output, the volume control is

inactive, and the 50-kHz lowpass filter is not available. The user has selection of different internal filter configurations.

Refer to Section 7.4.8 for details on the filter configuration control register.

4.2.2

Wideband Flatness Mode

The CS43198 specifically optimizes for wideband flatness playback, which is enabled by PCM_WBF_EN bit. This mode

should only be enabled when PCM plays back at 192 kHz. When operating in other speeds or modes, this bit should be

properly disabled. If wideband flatness mode enabled, the filter spec complies to Table 3-8. There is no option for filter

roll-off or phase response in this mode. NOS filter mode should be disabled for proper operation. Note that wideband

flatness mode can only be enabled or disabled when PDN_HP is set.

4.2.3

Mono Mode

The CS43198 supports mono (differential) mode playback. Mono mode allows driving a differential interconnect such as

a XLR connector or implementing a stereo differential headphone utilizing two CS43198 devices. Fig. 2-2 shows a typical

connection of the CS43198 to a XLR connector in mono mode.

4.3 Class H Output

Fig. 4-2 shows the Class H operation.

Figure 4-2. Class H Operation

The CS43198 outputs use Cirrus Logic two-mode Class H technology. This prevents unnecessarily wasting energy during

low power passages of program material or when the program material is played back at a low volume level.

The internal charge pump is the central component of the two-mode Class H technology implemented in the CS43198.

The charge pump receives its input voltage from the voltage present on the VCP or VP pin. From this input voltage, the

charge pump creates the differential rail voltages supplied to the output stages. The charge pump can supply two sets of

differential rail voltages: ±VCP and ±VP_LDO.

VCP

Class H Control

VCP_FILT–

–VCP

–VP_LDO V

VCP_FILT+

+VCP

+VP_LDO V

ADPT_PWR p. 114

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