CS43198 datasheet(51/137 Pages) CIRRUS

51 / 137 page

DS1156F1

CS43198

4.12 Control Port Operation

The control port is used to access control registers and on-chip memory locations, allowing the device to be configured for

desired operational modes and formats. Control port operation may be completely asynchronous with respect to the audio

sample rates. However, to avoid potential interference problems, control port pins must remain static if no operation is

required.

The control port operates using a I2C interface with the CS43198 acting as a slave device. Device communication must

not begin until tPUD (refer to Table 3-20) after power conditions are ready and RESET is released.

4.12.1 I2C Control Port Operation

The I2C control port operates completely asynchronously with the audio sample rates. However, to avoid interference

problems, the I2C control-port pins must remain static if no operation is required.

The control-port uses the I2C interface, with the chip acting as a slave device. The I2C control port can operate in the

following modes:

• Standard Mode (SM), with a bit rate of up to 100 kbit/s

• Fast Mode (FM), with a bit rate of up to 400 kbit/s

• Fast Mode Plus (FM+), with a bit rate of up to 1 Mbit/s

SDA is a bidirectional data line. Data is clocked into and out of the CS43198 by the SCL clock. Fig. 4-29, Fig. 4-30, and

Fig. 4-31 show signal timings for read and write cycles. A Start condition is defined as a falling transition of SDA while SCL

is high. A stop condition is defined as a rising transition of SDA while SCL is high. All other transitions of SDA must occur

while SCL is low. Note that when HP_IN_LP is set, only SM and FM modes are supported.

To configure the last two bits of I2C address, CS43198 detects the ADR resistor connection type and measures the

resistance upon a device power up (POR event) or after a hardware reset event (RESET deasserted). Based on the

detected resistance, the I2C address is latched and cannot be changed until the next hardware reset event. The I2C

address configuration is not ready until tPUD after the hardware reset event. During this period, the CS43198 does not

respond to any user-issued I2C command. After configuration, the IC tristates the ADR pin and becomes high impedance

internally to avoid a constant bias current.

ASP overload

ASP_OVLD_INT

ASP_OVLD_INT_MASK

ASP error

ASP_ERR_INT

ASP_ERR_INT_MASK

ASP late

ASP_LATE_INT

ASP_LATE_INT_MASK

ASP early

ASP_EARLY_INT

ASP_EARLY_INT_MASK

ASP no LRCK

ASP_NOLRCK_INT

ASP_NOLRCK_INT_MASK

XSP overload

XSP_OVLD_INT

XSP_OVLD_INT_MASK

XSP error

XSP_ERR_INT

XSP_ERR_INT_MASK

XSP late

XSP_LATE_INT

XSP_LATE_INT_MASK

XSP early

XSP_EARLY_INT

XSP_EARLY_INT_MASK

XSP no LRCK

XSP_NOLRCK_INT

XSP_NOLRCK_INT_MASK

PLL is ready

PLL_READY_INT

PLL_READY_INT_MASK

PLL error detected

PLL_ERROR_INT

PLL_ERROR_INT_MASK

Power down done

PDN_DONE_INT

PDN_DONE_INT_MASK

DSD stuck Error

DSD_STUCK_INT

DSD_STUCK_INT_MASK

DSD channel A invalid error

DSD_INVAL_A_INT

DSD_INVAL_A_INT_MASK

DSD channel B invalid error

DSD_INVAL_B_INT

DSD_INVAL_B_INT_MASK

DSD channel A silence pattern detected

DSD_SILENCE_A_INT

DSD_SILENCE_A_INT_MASK

DSD channel B silence pattern detected

DSD_SILENCE_B_INT

DSD_SILENCE_B_INT_MASK

DSD rate error detected

DSD_RATE_INT

DSD_RATE_INT_MASK

DoP marker detected

DOP_MRK_DET_INT

DOP_MRK_DET_INT_MASK

DoP engine on

DOP_ON_INT

DOP_ON_INT_MASK

Table 4-11. Interrupts Events and Register Bit Fields (Cont.)

Interrupt

Interrupt Mask Field

CS43198 Datasheet(PDF) 51 Page - Cirrus Logic

CS43198 Datasheet(HTML) 51 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL