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CS43198 Datasheet(PDF) 53 Page - Cirrus Logic

Part # CS43198
Description  130-dB, 32-Bit High-Performance DAC with Pseudodifferential Outputs
PDF  137 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43198 Datasheet(HTML) 53 Page - Cirrus Logic

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DS1156F1
53
CS43198
4.12 Control Port Operation
For read operations, the contents of the register pointed to by the last received MAP address (plus however many
autoincrements have occurred if INCR was previously set) are output in the next byte. Fig. 4-30 shows a read pattern
following the write pattern in Fig. 4-29. Notice how read addresses are based on the MAP bytes from Fig. 4-29.
Figure 4-30. Control Port Timing, I2C Reads with Autoincrement (8-Bit Data Access)
To generate a read address not based on the last received MAP address, an aborted write operation can be used as a
preamble (see Fig. 4-31). Here, a write operation is aborted (after the ACK for the control byte) by sending a Stop
condition.
Figure 4-31. Control Port Timing, I2C Reads with Preamble and Autoincrement (8-Bit Data Access)
SCL
CHIP ADDRESS
(READ)
START
SDA
SDA
Source
Master
Pull-up
Slave
Pull-up
ACK
4
5
6 7 8
9
17
0
1
2
3
7 6 5 4 3 2 1 0
ACK
NACK
7
0
7
0
16
DATA
BYTE 1
DATA
BYTE N
M
M
Slave
STOP
MAP
ADDRESS
MAP
ADDRESS
+ (N–1 )
Addr = 01100
SCL
CHIP ADDRESS
(WRITE)
MAP BYTE
High (23:16)
START
STOP
ACK
SDA
SDA
Source
Master
Master
Master
Pull-up
Slave
Slave
Pull-up
ACK
Addr = 01100
4
5
6 7 8
9
17 18
0
1
2
3
7 6 5 4 3 2 1 0
ACK
34
MAP BYTE
Mid (15:8)
MAP BYTE
Low (7:0)
36
ACK
ACK
CONTROL
BYTE
7 6 5 4 3 2 1 0
37 38
35
Empty
7
0
7
0
7
0
16
26 27
25
39 40 41 42 43 44
7
0
7
0
45
DATA
BYTE 1
DATA
BYTE N
Master
Master
Slave
Slave
Slave
M
Slave
START
7 6 5 4 3 2 1 0
ACK
ACK
M
NACK
STOP
Master
4
5
6 7 8
9
0
1
2
3
16 17
Slave
CHIP ADDRESS
(READ)
MAP
ADDRESS
MAP
ADDRESS
+ (N-1)
Addr = 01100



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