CS43198 datasheet(26/137 Pages) CIRRUS

26 / 137 page

DS1156F1

CS43198

4.1 Overview

• The clock generated by the CS43198 crystal oscillator.

• Output of the internal Fractional-N PLL that refers to MCLK input. See Section 4.6.1 for supported frequencies.

The internal MCLK is used to generate serial port clocks. See Table 4-6 for supported LRCK combinations.

4.1.5

System Interrupts

The CS43198 includes an open-drain interrupt output (INT pin). Interrupt mask registers control whether an event

associated with an interrupt status/mask bit pair triggers the assertion of INT. All types of interrupt are described in

Section 4.10.

4.1.6

System Reset

The CS43198 offers two types of reset options:

• Asserting RESET. If RESET is asserted, all registers and state machines are immediately set to their default values/

states. No operation can begin until RESET is deasserted. Before normal operation can begin, RESET must be

asserted at least once after the VP supply is first brought up.

• Power-on reset (POR). If the VD supply is lower than the POR threshold specified in Table 3-16, all registers and

state machines are set to their default values/states. The POR releases the reset when the VD supply goes above

the POR threshold. When the VD supply is turned on, the VL and VA supplies must also be turned on at the same

time.

4.1.7

Power Down

The CS43198 has a register to power down individual components on the chip. Before any change can be applied to an

individual component (except PLL), the block must be powered down first. For the PLL, changes can be applied after PLL_

START is cleared.

The PDN_HP bit is responsible for enabling or disabling the signal chain playback operation. Setting PDN_HP disables

signal chain playback operation. All the necessary components for playback operation need to be powered up and

configured properly before PDN_HP is cleared. PDN_HP needs to be set before making any changes to the playback

signal chain setup, except the following functions:

• Volume and mute related functions

• PCM filter settings (see Section 7.5.2)

Before ASP, XSP, or DSDIF can be safely powered down, PDN_HP must be asserted, and PDN_DONE_INT must be

present. For XTAL or PLL used as the source of internal MCLK, PDN_HP needs to be set first and MCLK source needs

to be properly switched away before PDN_XTAL or PDN_PLL is set. If PLL output is only used as the source of CLKOUT,

PDN_PLL can be set without PDN_HP being asserted. If the steps described above are not followed, the CS43198 enters

an unresponsive state.

PDN_CLKOUT does not require PDN_HP to be set before it is enabled.

Recommended power-up and power-down sequences can be found in the Section 5.2.

CS43198 Datasheet(PDF) 26 Page - Cirrus Logic