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CS43198 Datasheet(PDF) 29 Page - Cirrus Logic

Part # CS43198
Description  130-dB, 32-Bit High-Performance DAC with Pseudodifferential Outputs
PDF  137 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43198 Datasheet(HTML) 29 Page - Cirrus Logic

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DS1156F1
29
CS43198
4.3 Class H Output
HV_EN setting, as shown in Fig. 4-3, determines the VP_LDO voltage as shown in Table 4-1. HV_EN = 1 setting is
required to support the 1.7-V full-scale voltage. In this setting, minimum VP is required to be higher than 3.3 V. When HV_
EN = 0, the max output voltage is 1.4-V RMS full-scale voltage. In this setting, minimum VP is required to be higher than
3V.
Figure 4-3. Internal LDO Configuration
Table 4-2 shows the nominal signal and volume level ranges when the output is set to the adapt modes explained in
Section 4.3.1. If the signal level is greater than the maximum value of this range, then clipping can occur.
4.3.1
Power Supply Control Options
This section describes the two types of operation: standard Class AB and adapt-to-output signal. The set of rail voltages
supplied to the amplifier output stages depends on the ADPT_PWR (see p. 114) setting.
4.3.1.1 Standard Class AB Operation (ADPT_PWR = 001 or 010)
If ADPT_PWR is set to 001 or 010, the rail voltages supplied to the amplifiers are held to ±VP_LDO or ±VCP, respectively.
The rail voltages supplied to the output stages are held constant, regardless of the output signal level. The CS43198
outputs simply operate in a traditional Class AB configuration.
4.3.1.2 Adapt-to-Output Signal (ADPT_PWR = 111)
If ADPT_PWR is set to 111, the rail voltage sent to the output stages is based solely on whether the signal sent to the
amplifiers would cause the amplifiers to clip when operating on the lower set of rail voltages at certain threshold values.
• If it would cause clipping, the control logic instructs the charge pump to provide the next higher set of rail voltages
to the amplifiers.
• If it would not cause clipping, the control logic instructs the charge pump to provide the lower set of rail voltages to
the amplifiers, eliminating the need to advise the CS43198 of volume settings external to the device.
• Note that for Direct DSD Mode, ADPT_PWR = 111 mode is not supported.
Table 4-1. VP_LDO Voltage Per HV_EN Setting
HV_EN
VP_LDO Voltage
02.6 V
13.0 V
Table 4-2. Class H Supply Modes
Mode
Class H Supply Level
Signal 1 or Volume Level Range 2,3,
1.In adapt-to-signal, the volume level ranges are approximations but are within –0.5 dB from the values shown.
2.Relative to digital full scale with output gain set to 0 dB.
3.In fixed modes, clipping can occur if the signal level exceeds the maximum of this range due to setting the
supply too low.
0
±VP_LDO V, internally regulated from VP
 –11 dB
1
±VCP
< –11 dB
VP
VP_LDO
Internal
LDO
HV_EN p. 114



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