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CS43198 Datasheet(PDF) 16 Page - Cirrus Logic

Part # CS43198
Description  130-dB, 32-Bit High-Performance DAC with Pseudodifferential Outputs
PDF  137 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43198 Datasheet(HTML) 16 Page - Cirrus Logic

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16
DS1156F1
CS43198
3 Characteristics and Specifications
Table 3-6. Wideband Flatness Mode Analog Output Characteristics 1
Test conditions (unless otherwise specified): Fig. 2-1 shows CS43198 connections; input test signal is a 32-bit, full-scale 997-Hz sine wave (unless
specified otherwise); GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; ASP_M/Sb = 1; typical, min/max performance data taken with
VA = VCP = 1.8 V; VL = VD = 1.8 V; VP = 3.6 V; TA = +25°C; measurement bandwidth is 20 Hz–90 kHz; ASP_SPRATE = 0110 (LRCK = 192-kHz mode);
PDN_XTAL = 0, MCLK_INT = 1, and MCLK_SRC_SEL = 00 (crystal frequency fXTAL = 22.5792 MHz); Volume = 0 dB; when testing noise related
specifications (dynamic range, THD+N, idle channel noise), no external impedance on REFx.
1.This table also applies to external VCP_FILT supply mode: CS43198 power up procedure is per description in Section 5.12.1; EXT_VCPFILT = 1;
VCP_FILT+ and VCP_FILT– comply to
Table 3-2 when EXT_VCPFILT = 1; in this mode, HV_EN must be set to 1.
Wideband Flatness Mode Parameter 2,3
2.One LSB of triangular PDF dither is added to PCM data.
3.Referred to the typical full-scale voltage. Applies to all THD+N and dynamic range values in the table.
Minimum
Typical
Maximum
Units
AOUTx
RL = 600 
CL = 200 pF
OUT_FS = 11
Volume = 0 dB
+1dB_EN = 0
HV_EN = 1,
unless otherwise
specified
Dynamic range
(defined in Table 3-1)
24-bit, 32-bit
A-weighted
122
128
—
dB
THD+N (20 Hz–20 kHz,
defined in Table 3-1)
24-bit, 32-bit
0 dB
–20 dB
–60 dB
—
—
—
–112
–97
–67
–106
—
–61
dB
dB
dB
Idle channel noise
(A-weighted)
(defined in Table 3-1)
24-bit, 32-bit
—
0.69
—
µV
Full-scale output voltage
4.66
4.90
5.14
Vpp
Output power
—
5
—
mW
Interchannel isolation (defined in Table 3-1)
217 Hz
1 kHz
20 kHz
—
—
—
120
120
110
—
—
—
dB
dB
dB
AOUTx
RL = 600 
CL = 200 pF
OUT_FS = 11
Volume = 0 dB
+1dB_EN = 1
HV_EN = 1,
unless otherwise
specified
THD+N (20 Hz–20 kHz,
defined in Table 3-1)
24-bit, 32-bit
0 dB
—
–105
–99
dB
Full-scale output voltage
5.42
5.7
5.99
Vpp
Output power
—
6.8
—
mW
Other characteristics
for AOUTx
Interchannel gain mismatch (defined in Table 3-1)—
±0.1
—
dB
Interchannel phase mismatch (defined in Table 3-1)
—
—
±0.01
°
Output offset voltage: Mute (defined in Table 3-1)
—
±50
±100
µV
Gain drift (defined in Table 3-1)
—
±100
—
ppm/°C
Load resistance (RL)600
—
—
Load capacitance (CL)—
—
1
nF
Turn-on time (defined in Table 3-1)—
—
12
ms
Click/pop during PDN_HP enable or disable
A-weighted
—
±50
±100
µV
Table 3-7. Combined DAC Digital, On-Chip Analog and AOUTx Filter Characteristics
Test conditions (unless specified otherwise): The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired
sample rate by multiplying the given characteristic by Fs. Single-Speed Mode refers to 32-, 44.1-, and 48-kHz sample rates. Double-Speed Mode refers
to 88.2- and 96-kHz sample rates. Quad-Speed Mode refers to 176.4- and 192-kHz sample rates. Octuple-Speed Mode refers to 352.8- and 384-kHz
sample rates. MCLK_INT is an integer multiple of Fs; HPF disabled; no DC offset applied; group delay does not include serial port delay.
Parameter
Minimum Typical Maximum Units
Fast Roll-Off
(FILTER_SLOW_FASTB =0)
Single-Speed Mode 1
Passband 2
to –0.01-dB corner
to –3-dB corner
attenuation @ Fs/2
0
0
8.44 3
—
—
—
0.4535 4
0.482
—
Fs
Fs
dB
Passband ripple 10 Hz to –0.01-dB corner 5
–0.01
—
+0.01
dB
Stopband
0.547
—
—
Fs
Stopband attenuation 6
110
—
—
dB
Group delay (linear phase)
PHCOMP_LOWLATB = 1
—
39.5/Fs 7
—s
Group delay (minimum phase)
PHCOMB_LOWLATB = 0
—
6.3/Fs 8
—s
Deemphasis error 9
(Relative to 1 kHz)
Fs = 44.1 kHz
—
—
±0.3
dB



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