CS43198 datasheet(25/137 Pages) CIRRUS

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DS1156F1

CS43198

4 Functional Description

This section describes the general theory of operation of the CS43198, tracing the signal and control flow through the

various blocks within the device. It comprises the following sections:

• Section 4.1, “Overview”

• Section 4.2, “Analog Outputs”

• Section 4.3, “Class H Output”

• Section 4.4, “Headphone Presence Detect”

• Section 4.5, “Clocking Architecture”

• Section 4.6, “Clock Output and Fractional-N PLL”

• Section 4.7, “Filtering Options”

• Section 4.8, “Audio Serial Port (ASP)”

• Section 4.9, “DSD Interface”

• Section 4.10, “DSD and PCM Mixing”

• Section 4.11, “Standard Interrupts”

• Section 4.12, “Control Port Operation”

• Section 4.13, “Programmable Filter”

4.1 Overview

4.1.1

Analog Outputs

The analog output block includes separate pseudodifferential output. An on-chip inverting charge pump creates a positive

and negative voltage equal to the input, allowing an adaptable, full-scale output swing centered around ground. The

resulting internal supply can be ±VCP, or ±VP_LDO (either ±3.0 V with HV_EN = 1 or ±2.6 V with HV_EN = 0).

4.1.2

Headphone Detection

The CS43198 detects the presence of a headphone and notifies the application processor to wake up through an interrupt

event.

4.1.3

Audio Interfaces and Supported Formats

There are two serial input ports on the CS43198, the audio serial port (ASP) and the auxiliary serial port (XSP). The ASP

on the CS43198 supports I2S, TDM, and DoP (DSD over PCM) formats up to a 384-kHz sample rate. The XSP on the

CS43198 supports the DoP format up to a 352.8-kHz sample rate.

The CS43198 also has a dedicated DSD interface to support up to a 256•Fs DSD stream. The DSD interface shares pins

with the XSP.

4.1.4

System Clocking

The CS43198 internal MCLK can be sourced from three options:

• Direct MCLK/crystal mode. The internal MCLK is provided through XTI/MCLK pin directly or generated by crystal

oscillator.

• PLL mode. A PLL reference CLK is provided by externally through XTI/MCLK. The PLL is configured, and output is

used as the internal MCLK.

• RCO mode. An internal RCO is used as the internal MCLK. This mode can support HP detection and I2C

communication. DAC playback function is not supported.

The clock output is provided for audio applications that require high quality audio rate system clock. This clock output can

be sourced from the following two options:

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