CS43198 datasheet(19/137 Pages) CIRRUS

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DS1156F1

CS43198

3 Characteristics and Specifications

Table 3-10. DSD Combined Digital and On-Chip Analog Filter Response 1

Test conditions (unless specified otherwise): Digital gains are all set to 0 dB; TA = +25°C; PDN_XTAL = 0, MCLK_INT = 1, DSD_EN = 1, and MCLK_SRC_

SEL = 00 (crystal frequency fXTAL = 22.5792 MHz).

1.Filter response is by design.

Parameter

Minimum Typical Maximum Units

DSD Processor Mode

DIR_DSD = 0

Passband

to –3-dB corner

—

kHz

Frequency response 20 Hz to 20 kHz

–0.05

—

0.05

Roll-off

—

dB/Oct

Direct DSD Mode, 64•Fs, Low Gain,

DSD_SPEED = 00,

DSD_DIRECT_GAIN = 0, DIR_DSD = 1

Passband

to –0.1-dB corner

to –3-dB corner

—

7.8

kHz

Frequency response 20 Hz to 20 kHz

–0.67

—

Direct DSD Mode, 64•Fs, Low Gain

With Magnitude Compensation,

DSD_SPEED = 00,

DSD_DIRECT_GAIN = 0,

DSD_DIRECT_MC = 1, DIR_DSD = 1

Passband

to –0.1-dB corner

to –3-dB corner

—

kHz

Frequency response 20 Hz to 20 kHz

—

0.06

Direct DSD Mode, 64•Fs, High Gain,

DSD_SPEED = 00,

DSD_DIRECT_GAIN = 1, DIR_DSD = 1

Passband

to –0.1-dB corner

to –3-dB corner

—

7.5

kHz

Frequency response 20 Hz to 20 kHz

–0.71

—

Direct DSD Mode, 128•Fs, Low Gain,

DSD_SPEED = 01,

DSD_DIRECT_GAIN = 0, DIR_DSD = 1

Passband

to –0.1-dB corner

to –3-dB corner

—

7.8

kHz

Frequency response 20 Hz to 20 kHz

–0.67

—

Direct DSD Mode, 128•Fs, High Gain,

DSD_SPEED = 01,

DSD_DIRECT_GAIN = 1, DIR_DSD = 1

Passband

to –0.1-dB corner

to –3-dB corner

—

kHz

Frequency response 20 Hz to 20 kHz

–0.18

—

Table 3-11. Digital Interface Specifications and Characteristics

Test conditions (unless specified otherwise): Fig. 2-1 shows CS43198 connections; GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground;

parameters can vary with VL and VP; typical performance data taken with VP = 3.6 V, VCP = VA = 1.8 V, VD = 1.8V and VL = 1.8 V; min/max performance

data taken with VP = 3.6 V, VCP = VA = 1.8 V, VD = 1.8V and VL = 1.8 V; TA = +25°C; CL =60 pF.

Parameters 1

1.See Table 1-1 for serial and control-port power rails.

Symbol

Minimum Maximum Units

Input leakage current 2,3

2.Specification is per pin.

3.Includes current through internal pull-up or pull-down resistors on pin.

LRCK1, DSDB/LRCK2

SDIN1, SCLK1, DSDA/SDIN2, DSDCLK/SCLK2

SDA, SCL

INT, RESET

Iin

—

±4

±3

±100

µA

Internal weak pull-down

—

550

2450



Input capacitance

——

INT current sink (VOL = 0.3 V maximum)

—

825

—

µA

VL Logic (non-I2C)

High-level output voltage (IOH = –100 µA)

Low-level output voltage

High-level input voltage

Low-level input voltage

VOH

VOL

VIH

VIL

0.9•VL

—

0.7•VL

—

0.1•VL

—

0.3•VL

VL Logic (I2C only)

Hysteresis voltage (Fast Mode and Fast Mode Plus)

Low-level output voltage

High-level input voltage

Low-level input voltage

VHYS

VOL

VIH

VIL

0.05•VL

—

0.7•VL

—

0.2•VL

—

0.3•VL

HP_DETECT 4

4.The HP_DETECT input circuit allows the HP_DETECT signal to be as low of a voltage as VCP_FILT– and as high as VP. Section 4.4.1 provides

configuration details.

High-level input voltage

Low-level input voltage

VIH

VIL

0.93•VP

—

2.0

HP_DETECT current to VCP_FILT– 4

IHP_DETECT

1.00

2.91

µA

RESET pulse width low

—

1000

—

µs

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