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CS43198 Datasheet(PDF) 66 Page - Cirrus Logic |
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CS43198 Datasheet(HTML) 66 Page - Cirrus Logic |
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66 / 137 page  66 DS1156F1 CS43198 5.12 Example Sequences 16 Configure ASP frame ASP Frame Configuration. 0x40019 0x0A Reserved ASP_STP ASP_5050 ASP_FSD 000 0 1 010 Configure ASP port to accept I2S input 17 Set ASP channel location ASP Channel 1 Location. 0x50000 0x00 ASP_RX_CH1 0x00 ASP Channel 1 starts on SCLK0 ASP Channel 2 Location. 0x50001 0x00 ASP_RX_CH2 0x00 ASP Channel 2 starts on SCLK0 18 Set ASP channel size and enable ASP Channel 1 Size and Enable. 0x5000A 0x07 Reserved ASP_RX_CH1_AP ASP_RX_CH1_EN ASP_RX_CH1_RES 0000 0 1 11 ASP Channel 1 Active Phase ASP Channel 1 Enable ASP Channel 1 Size is 32 bits ASP Channel 2 Size and Enable. 0x5000B 0x0F Reserved ASP_RX_CH2_AP ASP_RX_CH2_EN ASP_RX_CH2_RES 0000 1 1 11 ASP Channel 2 Active Phase ASP Channel 2 Enable ASP Channel 2 Size is 32 bits 19 Configure PCM interface. HPF filter is used. Deemphasis off. 20 Configure PCM filter PCM Filter Option. 0x90000 0x02 FILTER_SLOW_FASTB PHCOMP_LOWLATB NOS Reserved PCM_WBF_EN HIGH_PASS DEEMP_ON 0 0 0 0 0 0 1 0 High pass filter is selected 21 Set volume for channel B PCM Volume B. 0x90001 0x00 PCM_VOLUME_B 0x00 Set volume to 0 dB 22 Set volume for channel A PCM Volume A. 0x90002 0x00 PCM_VOLUME_A 0x00 Set volume to 0 dB 23 Configure PCM path signal control PCM Path Signal Control 1. 0x90003 0xEC PCM_RAMP_DOWN PCM_VOL_BEQA PCM_SZC PCM_AMUTE PCM_AMUTEBEQA PCM_MUTE_A PCM_MUTE_B 1 1 10 1 1 0 0 Soft ramp down of volume on filter change Volume setting on both channels controlled by PCM_ VOLUME_A Enable soft ramp Mute after reception of 8192 samples of 0 or –1. Mute only when AMUTE condition is detected on both channels Function is disabled Function is disabled PCM Path Signal Control 2. 0x90004 0x00 Reserved PCM_INV_A PCM_INV_B PCM_SWAP_CHAN PCM_COPY_CHAN 0000 0 0 0 0 Disable all functions in this register 24 Configure DAC output 25 Configure Class H amplifierClass H Control. 0xB0000 0x1E Reserved ADPT_PWR HV_EN EXT_VCPFILT 000 1 11 1 0 Output signal determines voltage level High voltage mode enabled Using internal VCPFILT source. 26 Set DAC output to full scaleAnalog Output Control 1. 0x80000 0x30 Reserved Reserved OUT_FS Reserved Reserved Reserved +1dB_EN 0 0 11 0 0 0 0 Set DAC output to full scale (1.732 V rms) 27 Configure Headphone detect HP Detect. 0xD0000 0x04 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved 00 0 0 0 10 0 HP detect disabled HP detect input is not inverted Tip sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms Example 5-5. Startup to I2S Playback (Cont.) STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION |
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