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CS43198 Datasheet(PDF) 89 Page - Cirrus Logic

Part # CS43198
Description  130-dB, 32-Bit High-Performance DAC with Pseudodifferential Outputs
PDF  137 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43198 Datasheet(HTML) 89 Page - Cirrus Logic

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DS1156F1
89
CS43198
6 Register Quick Reference
6 Register Quick Reference
The registers for each CS43198 module are located at specific base addresses within the 24-bit register address space.
The organization of this register space is summarized in Table 6-1.
Notes: Default values are shown below the bit field names. The default values in all reserved bits must be preserved.
6.1 Global Registers
6.2 PLL Registers
Table 6-1. Register Base Addresses
Base Address
Module
Reference
0x01 0000
Global Registers
Section 6.1
0x03 0000
PLL Registers
Section 6.2
0x04 0000
ASP and XSP Registers
Section 6.3
0x06 0000
DSD Registers
Section 6.4
0x08 0000
Analog Output and PCM Registers
Section 6.5
0x0F 0000
Interrupt Status and Mask Registers
Section 6.6
Address
Function
7
654321
0
0x01 0000 Device ID A and B
(Read Only)
DEVIDA
DEVIDB
p. 96
0
100001
1
0x01 0001 Device ID C and D
(Read Only)
DEVIDC
DEVIDD
p. 96
0
001100
1
0x01 0002 Device ID E (Read
Only)
DEVIDE
—
p. 96
1
000000
0
0x01 0004 Revision ID (Read
Only)
AREVID
MTLREVID
p. 96
xxx
xxxxx
0x01 0005 Subrevision ID (Read
Only)
SUBREVID
p. 96
0
x
x
x
x
x
x
x
0x01 0006 System Clocking
Control
—
MCLK_INT
MCLK_SRC_SEL
p. 97
0
000011
0
0x01 0007–
0x01 000A
Reserved
—
0
000000
0
0x01 000B Serial Port Sample
Rate
—ASP_SPRATE
p. 97
0
000000
1
0x01 000C Serial Port Sample Bit
Size
—
XSP_SPSIZE
ASP_SPSIZE
p. 97
0
000010
1
0x01 000D Pad Interface
Configuration
—
XSP_3ST
ASP_3ST
p. 97
0
000001
1
0x01 000E–
0x01 FFFF
Reserved
—
0
000000
0
0x02 0000 Power Down Control
PDN_XSP
PDN_ASP
PDN_DSDIF
PDN_HP
PDN_XTAL
PDN_PLL
PDN_CLKOUT
—
p. 98
1
111111
0
0x02 0001–
0x02 0051
Reserved
—
0
000000
0
0x02 0052 Crystal Setting
—
XTAL_IBIAS
p. 98
00
0
0
0
1
0
0
0x02 0053–
0x03 0000
Reserved
—
0
000000
0
Address
Function
7
654321
0
0x03 0001 PLL Setting 1
—
PLL_START
p. 99
0
000000
0
0x03 0002 PLL Setting 2
PLL_DIV_FRAC_0
p. 99
0
000000
0
0x03 0003 PLL Setting 3
PLL_DIV_FRAC_1
p. 99
0
000000
0
0x03 0004 PLL Setting 4
PLL_DIV_FRAC_2
p. 99
0
000000
0



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