MEC1632 datasheet(171/636 Pages) MICROCHIP

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 2012-2018 Microchip Technology Inc.

DS00001592B-page 171

MEC1632

9.4.1

SIGNAL DESCRIPTION

9.4.2

HOST INTERFACE

The registers defined for the ACPI Embedded Controller Interface (ACPI-ECI) are accessible by the System Host and

the Embedded Controller as indicated in Section 9.11, "EC-Only Registers" and Section 9.10, "Runtime Registers".

9.5

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

9.5.1

POWER DOMAINS

9.5.2

CLOCK INPUTS

This block only requires the Host interface clocks to synchronize registers access.

9.5.3

RESETS

9.6

Interrupts

This section defines the Interrupt Sources generated from this block.

TABLE 9-2:

SIGNAL DESCRIPTION TABLE

Name

Direction

Description

EC_IBF

Output

Output follows IBF in STATUS OS-Register on page 179

EC_OBF

Output

Output follows inversion of OBF in STATUS OS-Register on page

179

TABLE 9-3:

POWER SOURCES

Name

Description

VTR

The logic and registers implemented in this block reside on this single power

well.

TABLE 9-4:

RESET SIGNALS

Name

Description

nSYS_RST

nSYS_RST resets all the logic and registers in ACPI Embedded Controller

Interface (ACPI-ECI).

TABLE 9-5:

INTERRUPTS

Source

Description

EC_OBF

EC_OBF interrupt is asserted when the OBF in the STATUS EC-Register is

cleared to ‘0’.

EC_IBF

EC_IBF interrupt is asserted when the IBF in the STATUS EC-Register is set

to ‘1’.

Note:

The usage model from the ACPI specification requires both SMI’s and SCI’s. The ACPI_OS SMI & SCI

interrupts are not implemented in the ACPI Embedded Controller Interface (ACPI-ECI). The SMI_EVT and

SCI_EVT bits in the Section 9.10.6, "STATUS OS-Register," on page 179 are software flags and this block

does not initiate SMI or SCI events.

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