MEC1632 datasheet(169/636 Pages) MICROCHIP

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 2012-2018 Microchip Technology Inc.

DS00001592B-page 169

MEC1632

8.6.15

HOST CLEAR ENABLE REGISTER

This register is accessible to the EC only.

HOST_CLR_ENABLE[14:0]

When a bit in this field is ‘0b’, the corresponding bit in the Interrupt Source Register cannot be cleared by writes to the

Interrupt Source Register. When a bit in this field is ‘1b’, the corresponding bit in the Interrupt Source Register can be

cleared when that register bit is written with a ‘1b’.

These bits allow the EC to control whether the status bits in the Interrupt Source Register are based on an edge or level

event.

TABLE 8-19:

HOST CLEAR ENABLE REGISTER

HOST OFFSET

N/A

N/A HOST SIZE

EC OFFSET

116h

16-Bit EC SIZE

POWER

VTR

0000h nSYS_RST DEFAULT

BUS

LPC SPB

BYTE1 BIT

D15

D14

D13

D12

D11

D10

HOST TYPE

-------

EC TYPE

R/W

BIT NAME

Host_Clr_Enable[14:7]

BYTE0 BIT

D7D6D5D4D3D2D1

HOST TYPE

-------

EC TYPE

R/W

BIT NAME

Host_Clr_Enable[6:0]

Reserved

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