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AT25SL321 Datasheet(PDF) 29 Page - Renesas Technology Corp |
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AT25SL321 Datasheet(HTML) 29 Page - Renesas Technology Corp |
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29 / 82 page ![]() DS-AT25SL321-112 Rev. J Page 29 Nov 1, 2022 © 2022 Renesas Electronics AT25SL321 Datasheet 8.11 Fast Read Dual Output (3Bh) By using two pins (IO0 and IO1, instead of just IO0), the Fast Read Dual Output command allows data to be transferred from the AT25SL321 at twice the rate of standard SPI devices. The Fast Read Dual Output command is ideal for quickly downloading code from Flash to RAM upon power-up or for application that cache code- segments to the RAM for execution. The Fast Read Dual Output command can operate at the highest possible frequency of FR (see Section 9.8, AC Electrical Characteristics). After the 24-bit address, eight dummy clocks are inserted to allow the internal circuits time set up the initial address. During the dummy clocks, the data value on the SO pin is a don’t care. However, the IO0 pin is going to be high-impedance prior to the falling edge of the first data out clock. This is shown in Figure 17. Figure 17. Fast Read Dual Output Command (SPI Mode) SCK CS SI SO 1 0 234 6 579 810 28 23 22 21 3 2 1 0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 High-Impedance 24-Bit Address Command 3Bh SCK CS SI SO High-Impedance Dummy Clocks Data Byte 1 Data Byte 2 75 3 1 64 2 0 75 3 1 64 2 0 |
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