AT25SL321 datasheet(25/82 Pages) RENESAS

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DS-AT25SL321-112 Rev. J

Page 25

Nov 1, 2022

AT25SL321 Datasheet

8.6

Write Status Register (01h)

The Write Status Register command is to write the non-volatile Status Register-1 bit (SRP0) and Status

Write Status Register command.

A Write Enable (06h) command must have been previously issued prior to setting Write Status Register

Command (Status Register bit WEL = 1). Once the write is enabled, the command is entered by driving CS low,

sending the command code, and then writing the status register data byte as illustrated in Figure 9 and Figure 10.

The CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the

Write Status Register command can not be executed. If CS is driven high after the eighth clock, hardware clears

the CMP, QE and SRP1 bits to 0. After CS is driven high, the self- timed Write Status Register cycle commences

for a time duration of tw (See Section 9.8, AC Electrical Characteristics).

While the Write Status Register cycle is in progress, the Read Status Register command can still be accessed to

check the status of the BUSY bit. The BUSY bit is set during the Write Status Register cycle and cleared

when the cycle is finished to indicate the device is ready to accept other commands. When the BUSY bit is

asserted, the Write Enable Latch (WEL) bit in Status Register is cleared to 0.

Figure 9. Write Status Register Command (SPI Mode)

Figure 10. Write Status Register Command (QPI Mode)

SCK

Mode 3

Mode 0

Mode 3

Mode 0

MSB

Status Register-1 in

Command

01h

High-Impedance

MSB

Status Register-2 in

SCK

Command

01h

SR1

SR2

Mode 3

Mode 0

Mode 3

Mode 0

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