AT25SL321 datasheet(16/82 Pages) RENESAS

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DS-AT25SL321-112 Rev. J

Page 16

Nov 1, 2022

AT25SL321 Datasheet

7.3

Status Register Protect (SRP1, SRP0)

The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the Status register (S8

and S7). The SRP bits control the method of write protection. These include software protection, hardware

protection, power supply lock-down or one time programmable (OTP) protection.

Note: When SRP1, SRP0 = (1,0), a power down, power-up cycle changes SRP1, SRP0 = (0,0).

7.4

Quad Enable (QE)

The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad

operation. When the QE bit is set to a 0 state (factory default) the WP pin and HOLD are enabled. When the QE

pin is set to a 1 the Quad IO2 and IO3 pins are enabled. WARNING: Never set the QE bit to a 1 during standard

SPI or Dual SPI operation if the WP or HOLD pins are tied directly to the power supply or ground.

7.5

Erase/Program Suspend Status (SUS)

The Suspend Status bit (SUS) is a read only bit in the status register (S15) that is set to 1 after executing an

Erase/Program Suspend (75h) command. The SUS status bit is cleared to 0 by Erase/Program Resume (7Ah)

command as well as a power down, power-up cycle.

Table 4. Encoding of the SRP[1:0] Bits in the Status Register

SRP1

SRP0

Status Register

Description

Software Protected

The register can be written to after a Write Enable command, WEL = 1.

[Factory Default]

Hardware Protected

When WP pin is low the Status Register locked and can not be written to.

Hardware Unprotected

When WP pin is high the Status register is unlocked and can be written

to after a Write Enable command, WEL=1.

Power Supply

Lock-Down

Status Register is protected and cannot be written to again until the next

power down, power-up cycle(1)

One-Time Program

Status Register is permanently protected and cannot be written to.

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