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AT25SL321 Datasheet(PDF) 27 Page - Renesas Technology Corp

Part # AT25SL321
Description  32-Mbit, 1.7 V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O, and QPI Support
PDF  82 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

AT25SL321 Datasheet(HTML) 27 Page - Renesas Technology Corp

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DS-AT25SL321-112 Rev. J
Page 27
Nov 1, 2022
© 2022 Renesas Electronics
AT25SL321 Datasheet
8.8
Read Data (03h)
The Read Data command is used to read data out from the memory. The command is initiated by driving the CS
pin low and then sending the command code 03h, followed by a 24-bit address (A23- A0), onto the SI pin. After
the address is received, the data byte of the addressed memory location is shifted out on the SO pin at the falling
edge of SCK with the most significant bit (MSB) first. The address is automatically incremented to the next higher
address after byte of data is shifted out allowing for a continuous stream of data. This means that the entire
memory can be accessed with a single command as long as the clock continues.
The command is completed by driving CS high. The Read Data command sequence is shown in Figure 13. If a
Read Data command is issued while an Erase, Program or Write Status Register cycle is in process (BUSY = 1)
the command is ignored and does not have any effect on the current cycle. The Read Data command allows clock
rates from D.C. to a maximum of fR (see Section 9.8, AC Electrical Characteristics).
Figure 13. Read Data Command
8.9
Fast Read (0Bh)
The Fast Read command can operate at the highest possible frequency of FR. The OBh command is driven onto
the SI pin, followed by the 24-bit address, and is latched on the rising edge of SCK. The address is then followed
by 8 dummy clocks as shown in Figure 14. The dummy clocks allows the internal circuits time to set up the initial
address. During the dummy clocks, the data value on the SO pin is a don’t care. Data of each bit shifts out on the
falling edge of SCK.
Figure 14. Fast Read Command (SPI Mode)
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DATA BYTE 1
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SCK
CS
1
0
234
6
579
810
28
23
22
21
3
2
1
0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
High-Impedance
24-Bit Address
Command
0Bh
SCK
CS
High-Impedance
Dummy Clocks
Data Out
76
5
4
32
1
0
Mode 3
Mode 0
SI
SO
SI
SO



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