AT25SL321 datasheet(43/82 Pages) RENESAS

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DS-AT25SL321-112 Rev. J

Page 43

Nov 1, 2022

AT25SL321 Datasheet

8.20 Chip Erase (C7h / 60h)

The Chip Erase command clears all bits in the device to be FFh (all 1s). Prior to the Chip Erase Command, a

Write Enable command must be issued. The command is initiated by driving the CS pin low and shifting the

command code C7h or 60h. (See Figure 35). The CS pin must go high after the eighth bit of the last byte has

been latched in; otherwise, the Chip Erase command can not be executed. After CS is driven high, the self-timed

Chip Erase command commences for a duration of tCE. See Section 9.8, AC Electrical Characteristics.

While the Chip Erase cycle is in progress, the Read Status Register command can still be accessed to check the

status of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when the cycle is

finished and the device is ready to accept other commands again. When the BUSY bit is asserted, the Write

Enable Latch (WEL) bit in the Status Register is cleared to 0.

Figure 35. Chip Erase Command for SPI Mode (left) and QPI Mode (right)

246

Mode 3

Mode 0

Mode 3

Mode 0

High-Impedance

SCK

Command (C7h/60h)

Command

(C7h/60h)

Mode 3

Mode 0

Mode 3

Mode 0

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