AT25SL321 datasheet(42/82 Pages) RENESAS

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DS-AT25SL321-112 Rev. J

Page 42

Nov 1, 2022

AT25SL321 Datasheet

8.19 64 kB Block Erase (D8h)

The Block Erase command is to erase the data of the selected block as being 1. The command is used for 64K-

byte Block erase operation. Prior to the Block Erase Command, a Write Enable command must be issued. The

command is initiated by driving the CS pin low and shifting the command code D8h followed a 24-bit block

address (A23-A0). (See Figure 33 and Figure 34). The CS pin must go high after the eighth bit of the last byte

has been latched in, otherwise, the Block Erase command can not be executed. After CS is driven high, the self-

timed Block Erase command commences for a time duration of tBE2. See Section 9.8, AC Electrical

Characteristics.

While the Block Erase cycle is in progress, the Read Status Register command can still be read the status of

the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished

and the device is ready to accept other commands again. When the BUSY bit is asserted, the Write Enable

Latch (WEL) bit in the Status Register is cleared to 0.

Figure 33. 64 kB Block Erase Command (SPI Mode)

Figure 34. 64 kB Block Erase Command (QPI Mode)

246

Mode 3

Mode 0

Mode 3

Mode 0

High-Impedance

SCK

Command (D8h)

24-Bit Address

MSB

SCK

2345

Mode 3

Command

D8h

A23-16

A15-8

A7-0

Mode 0

Mode 3

Mode 0

MSB

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